Barnabás Czémán f973db0464 clk/qcom/clk-alpha-pll: Fix pll post div mask when width is not set ...

Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c35411 ("clk: qcom: support for 2 bit PLL post divider")
Change-Id: I8e4fa923b1183a14c7893f08597a8289f8c3e3b8
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20241006-fix-postdiv-mask-v3-1-160354980433@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

2025-03-30 23:53:37 +01:00

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clk/qcom/clk-alpha-pll: Fix pll post div mask when width is not set

2025-03-30 23:53:37 +01:00

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