ARM: dts: msm: Add npu mailbox controller support for lito

The mailbox controller implemented in NPU works as a bridge
between ipcc_mproc mailbox controller and its clients. It is
required because npu driver needs to control when IPCC irq can
be sent to NPUQ6.

Change-Id: I1b779ae0ddf98149f0792a13144069695f29bc1e

qcom/lito-npu.dtsi

@@ -69,13 +69,19 @@
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
 		qcom,proxy-reg-names ="vdd", "vdd_cx";
 		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
-		mboxes = <&qmp_aop 0>;
-		mbox-names = "aop";
 		resets = <&npucc NPU_CC_DPM_TEMP_CLK_ARES>,
 				<&npucc NPU_CC_LLM_CURR_CLK_ARES>,
 				<&npucc NPU_CC_LLM_TEMP_CLK_ARES>;
 		reset-names = "dpm_temp_clk", "llm_curr_clk", "llm_temp_clk";
 		#cooling-cells = <2>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
+				IPCC_MPROC_SIGNAL_GLINK_QMP>,
+			<&ipcc_mproc IPCC_CLIENT_NPU
+				IPCC_MPROC_SIGNAL_SMP2P>,
+			<&ipcc_mproc IPCC_CLIENT_NPU
+				IPCC_MPROC_SIGNAL_PING>;
+		mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
+		#mbox-cells = <2>;
 		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
 		qcom,npu-pwrlevels {
 			#address-cells = <1>;

qcom/lito-smp2p.dtsi

@@ -127,7 +127,7 @@
 		interrupt-parent = <&ipcc_mproc>;
 		interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
 			      IRQ_TYPE_EDGE_RISING>;
-		mboxes = <&ipcc_mproc IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
+		mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
 		qcom,local-pid = <0>;
 		qcom,remote-pid = <10>;
 

qcom/lito.dtsi

@@ -2607,7 +2607,7 @@
 		glink_npu: npu {
 			qcom,remote-pid = <10>;
 			transport = "smem";
-			mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
+			mboxes = <&msm_npu IPCC_CLIENT_NPU
 				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
 			mbox-names = "npu_smem";
 			interrupt-parent = <&ipcc_mproc>;