dts/Devon4G:add PVT dts to support different disp configs for DVT/PVT

Devon4G
add PVT dts to support different display configs for DVT/PVT

Change-Id: Id6782bf5d9d72e93d8abd182f1b0c119246bb2db
Signed-off-by: hujing3 <hujing3@lenovo.com>
Reviewed-on: https://gerrit.mot.com/2276413
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Nan Wu <wunan3@motorola.com>
Reviewed-by: Jianguo Liu <liujg6@motorola.com>
Reviewed-by: Wang Wang <wangwang1@lenovo.com>
Submit-Approved: Jira Key
This commit is contained in:
hujing3 authored and Carlos Pinho committed 2023-05-31 17:01:06 -03:00
1 parent 1bae99c319
commit c18930608f
2 files changed
+55 -1

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+3 -1
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@@ -93,10 +93,12 @@ khaje-hawao-evt-overlay.dtbo-base := khaje-moto-base.dtb
dtbo-$(CONFIG_DEVON_DTB) += \
khaje-devon-evt-overlay.dtbo \
khaje-devon-dvt2-overlay.dtbo
khaje-devon-dvt2-overlay.dtbo \
khaje-devon-pvt-overlay.dtbo
khaje-devon-evt-overlay.dtbo-base := khaje-moto-base.dtb
khaje-devon-dvt2-overlay.dtbo-base := khaje-moto-base.dtb
khaje-devon-pvt-overlay.dtbo-base := khaje-moto-base.dtb
else
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+52
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@@ -0,0 +1,52 @@
/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/plugin/;
#include "khaje-devon-common-overlay.dtsi"
#include "khaje-devon-audio-overlay.dtsi"
/ {
model = "devon";
compatible = "qcom,khaje-devon", "qcom,khaje-moto", "qcom,khaje";
qcom,msm-id = <518 0x10000>;
qcom,board-id = <0 0xC000>;
};
&qupv3_se2_i2c {
status = "ok"
aw9610x_sar@12 {
compatible = "awinic,aw9610x_sar_0";
reg = <0x12>;
sar-gpio-vcc-enable;
sar-gpio_3v0_en = <&tlmm 67 0x00>;
pinctrl-names = "default";
pinctrl-0 = <&capsense_sar_gpio_pins>;
interrupt-parent = <&tlmm>;
interrupts = <106 0x02>;
irq-gpio = <&tlmm 106 0x02>;
chip_name = "AW96105";
sar-num = <0>;
cap_vcc-supply = <&pm6125_l21>;
aw9610x,channel_number = <0x5>;
ch0_name = "Ch0capsense_reference";
ch1_name = "Ch1capsense_top_left";
ch2_name = "Ch2capsense_top_right";
ch3_name = "Ch3capsense_reference";
ch4_name = "Ch4capsense_bottom";
ref_channel = <0x9>;
hardware_version = <1>;
aw9610x,using-firmware;
aw9610x,firmware_name = "aw9610x_0";
};
};