disp: msm: dp: disable ASSR before link training

Power on reset value of DPTX_CONFIGURATION_CTRL.ASSR (alternate scrambler
seed reset) is high. This fails link training 2 with TPS4 pattern.
Change disables this before link training starts.

Change-Id: Iee95de04625658254b242afdcbba6db24a52606d
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Navjyot SINGH <quic_navjsing@quicinc.com>

msm/dp/dp_catalog.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 
@@ -986,7 +987,12 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt)
 	io_data = catalog->io.dp_link;
 
 	cfg = dp_read(DP_CONFIGURATION_CTRL);
-	cfg &= ~(BIT(4) | BIT(5));
+	/*
+	 * Reset ASSR (alternate scrambler seed reset) by resetting BIT(10).
+	 * ASSR should be set to disable for TPS4 link training pattern.
+	 * Forcing it to 0 as the power on reset value of register enables it.
+	 */
+	cfg &= ~(BIT(4) | BIT(5) | BIT(10));
 	cfg |= (ln_cnt - 1) << 4;
 	dp_write(DP_CONFIGURATION_CTRL, cfg);