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Merge tag 'v4.19.325-cip133' of https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip into android13-4.19-kona

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version 4.19.325-cip133

* tag 'v4.19.325-cip133' of https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip:
  CIP: Bump version suffix to -cip133 after merge from cip/linux-4.19.y-st tree
  Update localversion-st, tree is up-to-date with 5.10.256.
  x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache
  x86/CPU/AMD: Add X86_FEATURE_ZEN1
  x86/CPU/AMD: Rename init_amd_zn() to init_amd_zen_common()
  x86/CPU/AMD: Add ZenX generations flags
  ptrace: slightly saner 'get_dumpable()' logic
  xfrm: esp: avoid in-place decrypt on shared skb frags

Change-Id: Ia30897652093bba532efb6a1d13f5384364b5348
This commit is contained in:
Thomas Turner committed 2026-05-31 11:19:50 +01:00
2 parents 4908d99742 9cd7882c4f
commit 543813ab78
13 files changed
+116 -15
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arch/x86/include/asm/cpufeatures.h
+6 -1
View File
@@ -218,7 +218,7 @@
#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
@@ -294,6 +294,11 @@
#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
#define X86_FEATURE_MSR_TSX_CTRL (11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
#define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
#define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
#define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
#define X86_FEATURE_ZEN1 (11*32+31) /* "" CPU based on Zen1 microarchitecture */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
arch/x86/include/asm/msr-index.h
+1
View File
@@ -455,6 +455,7 @@
/* Zen4 */
#define MSR_ZEN4_BP_CFG 0xc001102e
#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
/* Fam 17h MSRs */
#define MSR_F17H_IRPERF 0xc00000e9
arch/x86/kernel/cpu/amd.c
+77 -3
View File
@@ -641,6 +641,49 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
}
}
/* Figure out Zen generations: */
switch (c->x86) {
case 0x17: {
switch (c->x86_model) {
case 0x00 ... 0x2f:
case 0x50 ... 0x5f:
setup_force_cpu_cap(X86_FEATURE_ZEN1);
break;
case 0x30 ... 0x4f:
case 0x60 ... 0x7f:
case 0x90 ... 0x91:
case 0xa0 ... 0xaf:
setup_force_cpu_cap(X86_FEATURE_ZEN2);
break;
default:
goto warn;
}
break;
}
case 0x19: {
switch (c->x86_model) {
case 0x00 ... 0x0f:
case 0x20 ... 0x5f:
setup_force_cpu_cap(X86_FEATURE_ZEN3);
break;
case 0x10 ... 0x1f:
case 0x60 ... 0xaf:
setup_force_cpu_cap(X86_FEATURE_ZEN4);
break;
default:
goto warn;
}
break;
}
default:
break;
}
return;
warn:
WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
}
static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
@@ -951,9 +994,14 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
clear_rdrand_cpuid_bit(c);
}
static void init_amd_zn(struct cpuinfo_x86 *c)
static void init_amd_zen_common(void)
{
set_cpu_cap(c, X86_FEATURE_ZEN);
setup_force_cpu_cap(X86_FEATURE_ZEN);
}
static void init_amd_zen1(struct cpuinfo_x86 *c)
{
init_amd_zen_common();
/* Fix up CPUID bits, but only if not virtualised. */
if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) {
@@ -1027,6 +1075,24 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
}
}
static void init_amd_zen2(struct cpuinfo_x86 *c)
{
init_amd_zen_common();
if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT);
}
static void init_amd_zen3(struct cpuinfo_x86 *c)
{
init_amd_zen_common();
}
static void init_amd_zen4(struct cpuinfo_x86 *c)
{
init_amd_zen_common();
}
static void init_amd(struct cpuinfo_x86 *c)
{
early_init_amd(c);
@@ -1056,9 +1122,17 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
case 0x16: init_amd_jg(c); break;
case 0x17: init_amd_zn(c); break;
}
if (boot_cpu_has(X86_FEATURE_ZEN1))
init_amd_zen1(c);
else if (boot_cpu_has(X86_FEATURE_ZEN2))
init_amd_zen2(c);
else if (boot_cpu_has(X86_FEATURE_ZEN3))
init_amd_zen3(c);
else if (boot_cpu_has(X86_FEATURE_ZEN4))
init_amd_zen4(c);
/*
* Enable workaround for FXSAVE leak on CPUs
* without a XSaveErPtr feature
include/linux/sched.h
+3
View File
@@ -989,6 +989,9 @@ struct task_struct {
/* Unserialized, strictly 'current' */
/* Save user-dumpable when mm goes away */
unsigned user_dumpable:1;
/* Bit to tell LSMs we're in execve(): */
unsigned in_execve:1;
unsigned in_iowait:1;
kernel/exit.c
+1
View File
@@ -596,6 +596,7 @@ static void exit_mm(void)
BUG_ON(mm != current->active_mm);
/* more a memory barrier than a real lock */
task_lock(current);
current->user_dumpable = (get_dumpable(mm) == SUID_DUMP_USER);
current->mm = NULL;
mmap_read_unlock(mm);
enter_lazy_tlb(mm, current);
kernel/ptrace.c
+16 -6
View File
@@ -281,11 +281,24 @@ static bool ptrace_has_cap(struct user_namespace *ns, unsigned int mode)
return ns_capable(ns, CAP_SYS_PTRACE);
}
static bool task_still_dumpable(struct task_struct *task, unsigned int mode)
{
struct mm_struct *mm = task->mm;
if (mm) {
if (get_dumpable(mm) == SUID_DUMP_USER)
return true;
return ptrace_has_cap(mm->user_ns, mode);
}
if (task->user_dumpable)
return true;
return ptrace_has_cap(&init_user_ns, mode);
}
/* Returns 0 on success, -errno on denial. */
static int __ptrace_may_access(struct task_struct *task, unsigned int mode)
{
const struct cred *cred = current_cred(), *tcred;
struct mm_struct *mm;
kuid_t caller_uid;
kgid_t caller_gid;
@@ -346,11 +359,8 @@ ok:
* Pairs with a write barrier in commit_creds().
*/
smp_rmb();
mm = task->mm;
if (mm &&
((get_dumpable(mm) != SUID_DUMP_USER) &&
!ptrace_has_cap(mm->user_ns, mode)))
return -EPERM;
if (!task_still_dumpable(task, mode))
return -EPERM;
return security_ptrace_access_check(task, mode);
}
localversion-cip
+1 -1
View File
@@ -1 +1 @@
-cip132
-cip133
localversion-st
+1 -1
View File
@@ -1 +1 @@
-st16
-st17
net/ipv4/esp4.c
+2 -1
View File
@@ -728,7 +728,8 @@ static int esp_input(struct xfrm_state *x, struct sk_buff *skb)
nfrags = 1;
goto skip_cow;
} else if (!skb_has_frag_list(skb)) {
} else if (!skb_has_frag_list(skb) &&
!skb_has_shared_frag(skb)) {
nfrags = skb_shinfo(skb)->nr_frags;
nfrags++;
net/ipv4/ip_output.c
+2
View File
@@ -1340,6 +1340,8 @@ ssize_t ip_append_page(struct sock *sk, struct flowi4 *fl4, struct page *page,
goto error;
}
skb_shinfo(skb)->tx_flags |= SKBTX_SHARED_FRAG;
if (skb->ip_summed == CHECKSUM_NONE) {
__wsum csum;
csum = csum_page(page, offset, len);
net/ipv6/esp6.c
+2 -1
View File
@@ -640,7 +640,8 @@ static int esp6_input(struct xfrm_state *x, struct sk_buff *skb)
nfrags = 1;
goto skip_cow;
} else if (!skb_has_frag_list(skb)) {
} else if (!skb_has_frag_list(skb) &&
!skb_has_shared_frag(skb)) {
nfrags = skb_shinfo(skb)->nr_frags;
nfrags++;
tools/arch/x86/include/asm/cpufeatures.h
+1 -1
View File
@@ -218,7 +218,7 @@
#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
tools/testing/selftests/kvm/include/x86.h
+3
View File
@@ -642,6 +642,9 @@ void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_x86_state *s
#define MSR_AMD64_SEV_ENABLED_BIT 0
#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
#define MSR_ZEN4_BP_CFG 0xc001102e
#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT 33
/* Fam 17h MSRs */
#define MSR_F17H_IRPERF 0xc00000e9