Add cpu clock controller support for SDM429 and SDM439 targets. Change-Id: I0dd455dd1734ed083965878167f51dfef5051e19
258 lines
4.5 KiB
Devicetree
258 lines
4.5 KiB
Devicetree
#include "msm8917.dtsi"
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#include "qm215-camera.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. QM215";
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compatible = "qcom,qm215";
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qcom,msm-id = <386 0x0>;
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qcom,msm-name = "QM215";
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};
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/ {
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qrd_batterydata: qcom,batterydata {
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qcom,rpull-up-kohm = <100>;
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qcom,vref-batt-therm = <1800000>;
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#include "vbms-batterydata-mlp356477-2800mah.dtsi"
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};
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};
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&soc {
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qcom,vidc@1d00000 {
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qcom,allowed-clock-rates = <329140000 329140000
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308570000 270000000 200000000>;
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};
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};
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&gcc {
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compatible = "qcom,gcc-qm215", "syscon";
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};
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&msm_cpufreq {
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/delete-property/qcom,cpufreq-table;
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qcom,cpufreq-table =
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< 960000 >,
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< 1094400 >,
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< 1209600 >,
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< 1248000 >,
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< 1305600 >;
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};
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/* GPU overrides */
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&msm_gpu {
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qcom,gpu-speed-bin = <0x0164 0x00000600 9>;
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/delete-property/qcom,gpu-speed-bin-vectors;
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/delete-node/qcom,gpu-pwrlevel-bins;
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible="qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,initial-pwrlevel = <3>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <598000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <7>;
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qcom,bus-max = <7>;
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};
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/* NOM+ */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <523200000>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <484800000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <6>;
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};
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/* SVS+ */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <400000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <270000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* XO */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <1>;
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qcom,initial-pwrlevel = <2>;
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/* NOM+ */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <500000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <6>;
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qcom,bus-max = <7>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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/* SVS+ */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <400000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <270000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* XO */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <2>;
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qcom,initial-pwrlevel = <1>;
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/* NOM */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <465000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <7>;
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};
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/* SVS+ */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <400000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <5>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <270000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* XO */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <3>;
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qcom,initial-pwrlevel = <0>;
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/* SVS+ */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <400000000>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <3>;
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qcom,bus-max = <6>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <270000000>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* XO */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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};
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};
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&thermal_zones {
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gpu0-step {
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trips {
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gpu-step-trip {
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temperature = <85000>;
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};
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};
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};
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};
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