Rajeev Nandan
e82dc955a0
Remove extra space from "phy_base" reg-names of dsi pll node. Change-Id: I34d5a4ee28e272d69ee1dacadc373f723f5c16bf
21 lines
541 B
Devicetree
21 lines
541 B
Devicetree
&soc {
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mdss_dsi0_pll: qcom,mdss_dsi0_pll {
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compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x5e94900 0x264>,
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<0x5e94400 0x800>,
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<0x5f01004 0x8>,
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<0x5e94200 0x100>;
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reg-names = "pll_base", "phy_base",
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"gdsc_base", "dynamic_pll_base";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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memory-region = <&dfps_data_memory>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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};
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};
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