add hiamx tp support Change-Id: Ic25c96a8a01316531f470f845bc00ec71c76f708 Signed-off-by: dengwei1 <dengwei1@motorola.com> Reviewed-on: https://gerrit.mot.com/1508389 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Lu Lu <lulu2@lenovo.com> Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com> Submit-Approved: Jira Key
1230 lines
22 KiB
Devicetree
1230 lines
22 KiB
Devicetree
&soc {
|
|
tlmm: pinctrl@400000 {
|
|
compatible = "qcom,bengal-pinctrl";
|
|
reg = <0x400000 0xc00000>;
|
|
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
wakeup-parent = <&wakegpio>;
|
|
irqdomain-map = <0 0 &wakegpio 84 0>,
|
|
<3 0 &wakegpio 75 0>,
|
|
<4 0 &wakegpio 16 0>,
|
|
<6 0 &wakegpio 59 0>,
|
|
<8 0 &wakegpio 63 0>,
|
|
<11 0 &wakegpio 17 0>,
|
|
<13 0 &wakegpio 18 0>,
|
|
<14 0 &wakegpio 51 0>,
|
|
<17 0 &wakegpio 20 0>,
|
|
<18 0 &wakegpio 52 0>,
|
|
<19 0 &wakegpio 53 0>,
|
|
<24 0 &wakegpio 6 0>,
|
|
<25 0 &wakegpio 71 0>,
|
|
<27 0 &wakegpio 73 0>,
|
|
<28 0 &wakegpio 41 0>,
|
|
<31 0 &wakegpio 27 0>,
|
|
<32 0 &wakegpio 54 0>,
|
|
<33 0 &wakegpio 55 0>,
|
|
<34 0 &wakegpio 56 0>,
|
|
<35 0 &wakegpio 57 0>,
|
|
<36 0 &wakegpio 58 0>,
|
|
<39 0 &wakegpio 28 0>,
|
|
<46 0 &wakegpio 29 0>,
|
|
<62 0 &wakegpio 60 0>,
|
|
<63 0 &wakegpio 61 0>,
|
|
<64 0 &wakegpio 62 0>,
|
|
<65 0 &wakegpio 30 0>,
|
|
<66 0 &wakegpio 31 0>,
|
|
<67 0 &wakegpio 32 0>,
|
|
<69 0 &wakegpio 33 0>,
|
|
<70 0 &wakegpio 34 0>,
|
|
<72 0 &wakegpio 72 0>,
|
|
<75 0 &wakegpio 35 0>,
|
|
<79 0 &wakegpio 36 0>,
|
|
<80 0 &wakegpio 21 0>,
|
|
<81 0 &wakegpio 38 0>,
|
|
<83 0 &wakegpio 9 0>,
|
|
<84 0 &wakegpio 39 0>,
|
|
<85 0 &wakegpio 40 0>,
|
|
<86 0 &wakegpio 19 0>,
|
|
<87 0 &wakegpio 42 0>,
|
|
<88 0 &wakegpio 43 0>,
|
|
<89 0 &wakegpio 45 0>,
|
|
<91 0 &wakegpio 74 0>,
|
|
<93 0 &wakegpio 46 0>,
|
|
<94 0 &wakegpio 47 0>,
|
|
<95 0 &wakegpio 48 0>,
|
|
<96 0 &wakegpio 49 0>,
|
|
<97 0 &wakegpio 50 0>,
|
|
<99 0 &wakegpio 64 0>, /* LPI_GPIO 7 */
|
|
<102 0 &wakegpio 65 0>, /* LPI_GPIO 10 */
|
|
<103 0 &wakegpio 66 0>, /* LPI_GPIO 11 */
|
|
<104 0 &wakegpio 67 0>, /* LPI_GPIO 12 */
|
|
<105 0 &wakegpio 69 0>, /* LPI_GPIO 17 */
|
|
<106 0 &wakegpio 14 0>, /* LPI_GPIO 16 */
|
|
<107 0 &wakegpio 7 0>, /* LPI_GPIO 17 */
|
|
<109 0 &wakegpio 37 0>, /* LPI_GPIO 19 */
|
|
<112 0 &wakegpio 25 0>; /* LPI_GPIO 24 */
|
|
irqdomain-map-pass-thru = <0 0xff>;
|
|
irqdomain-map-mask = <0xff 0>;
|
|
|
|
ufs_dev_reset_assert: ufs_dev_reset_assert {
|
|
config {
|
|
pins = "ufs_reset";
|
|
bias-pull-down; /* default: pull down */
|
|
/*
|
|
* UFS_RESET driver strengths are having
|
|
* different values/steps compared to typical
|
|
* GPIO drive strengths.
|
|
*
|
|
* Following table clarifies:
|
|
*
|
|
* HDRV value | UFS_RESET | Typical GPIO
|
|
* (dec) | (mA) | (mA)
|
|
* 0 | 0.8 | 2
|
|
* 1 | 1.55 | 4
|
|
* 2 | 2.35 | 6
|
|
* 3 | 3.1 | 8
|
|
* 4 | 3.9 | 10
|
|
* 5 | 4.65 | 12
|
|
* 6 | 5.4 | 14
|
|
* 7 | 6.15 | 16
|
|
*
|
|
* POR value for UFS_RESET HDRV is 3 which means
|
|
* 3.1mA and we want to use that. Hence just
|
|
* specify 8mA to "drive-strength" binding and
|
|
* that should result into writing 3 to HDRV
|
|
* field.
|
|
*/
|
|
drive-strength = <8>; /* default: 3.1 mA */
|
|
output-low; /* active low reset */
|
|
};
|
|
};
|
|
|
|
ufs_dev_reset_deassert: ufs_dev_reset_deassert {
|
|
config {
|
|
pins = "ufs_reset";
|
|
bias-pull-down; /* default: pull down */
|
|
/*
|
|
* default: 3.1 mA
|
|
* check comments under ufs_dev_reset_assert
|
|
*/
|
|
drive-strength = <8>;
|
|
output-high; /* active low reset */
|
|
};
|
|
};
|
|
|
|
/* SDC pin type */
|
|
sdc1_clk_on: sdc1_clk_on {
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <16>; /* 16 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_clk_off: sdc1_clk_off {
|
|
config {
|
|
pins = "sdc1_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_on: sdc1_cmd_on {
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_cmd_off: sdc1_cmd_off {
|
|
config {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_data_on: sdc1_data_on {
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_data_off: sdc1_data_off {
|
|
config {
|
|
pins = "sdc1_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_on: sdc1_rclk_on {
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down; /* pull down */
|
|
};
|
|
};
|
|
|
|
sdc1_rclk_off: sdc1_rclk_off {
|
|
config {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down; /* pull down */
|
|
};
|
|
};
|
|
|
|
sdc2_clk_on: sdc2_clk_on {
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <16>; /* 16 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_clk_off: sdc2_clk_off {
|
|
config {
|
|
pins = "sdc2_clk";
|
|
bias-disable; /* NO pull */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_on: sdc2_cmd_on {
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cmd_off: sdc2_cmd_off {
|
|
config {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_data_on: sdc2_data_on {
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <10>; /* 10 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_data_off: sdc2_data_off {
|
|
config {
|
|
pins = "sdc2_data";
|
|
bias-pull-up; /* pull up */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
sdc2_cd_on: cd_on {
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_cd_off: cd_off {
|
|
mux {
|
|
pins = "gpio88";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio88";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
tb_trig1_on: tb_trig1_on {
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "SDC1_TB";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
bias-pull-up; /* PULL UP */
|
|
drive-strength = <8>; /* 8 MA */
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
/* WSA speaker reset pin1 */
|
|
spkr_1_sd_n {
|
|
spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
|
|
mux {
|
|
pins = "gpio106";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio106";
|
|
drive-strength = <2>; /* 2 mA */
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_1_sd_n_active: spkr_1_sd_n_active {
|
|
mux {
|
|
pins = "gpio106";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio106";
|
|
drive-strength = <16>; /* 16 mA */
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
wcd937x_reset_active: wcd937x_reset_active {
|
|
mux {
|
|
pins = "gpio92";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio92";
|
|
drive-strength = <16>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
wcd937x_reset_sleep: wcd937x_reset_sleep {
|
|
mux {
|
|
pins = "gpio92";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio92";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
|
|
qupv3_se4_2uart_active: qupv3_se4_2uart_active {
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "qup4";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
|
|
qupv3_se3_default_ctsrtsrx:
|
|
qupv3_se3_default_ctsrtsrx {
|
|
mux {
|
|
pins = "gpio8", "gpio9", "gpio11";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9", "gpio11";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_default_tx:
|
|
qupv3_se3_default_tx {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_ctsrx: qupv3_se3_ctsrx {
|
|
mux {
|
|
pins = "gpio8", "gpio11";
|
|
function = "qup3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio11";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_rts: qupv3_se3_rts {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_tx: qupv3_se3_tx {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
|
|
qupv3_se0_i2c_active: qupv3_se0_i2c_active {
|
|
mux {
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
|
|
mux {
|
|
pins = "gpio0", "gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
|
|
qupv3_se1_i2c_active: qupv3_se1_i2c_active {
|
|
mux {
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
|
|
mux {
|
|
pins = "gpio4", "gpio5";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
nfc {
|
|
nfc_int_active: nfc_int_active {
|
|
/* active state */
|
|
mux {
|
|
/* GPIO 70 NFC Read Interrupt */
|
|
pins = "gpio70";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_int_suspend: nfc_int_suspend {
|
|
/* sleep state */
|
|
mux {
|
|
/* GPIO 70 NFC Read Interrupt */
|
|
pins = "gpio70";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_enable_active: nfc_enable_active {
|
|
/* active state */
|
|
mux {
|
|
/* 69: Enable 31: Firmware */
|
|
pins = "gpio69", "gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69", "gpio31";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_enable_suspend: nfc_enable_suspend {
|
|
/* sleep state */
|
|
mux {
|
|
/* 69: Enable 31: Firmware */
|
|
pins = "gpio69", "gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69", "gpio31";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
nfc_clk_req_active: nfc_clk_req_active {
|
|
/* active state */
|
|
mux {
|
|
/* GPIO 86: NFC CLOCK REQUEST */
|
|
pins = "gpio86";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio86";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
nfc_clk_req_suspend: nfc_clk_req_suspend {
|
|
/* sleep state */
|
|
mux {
|
|
/* GPIO 86: NFC CLOCK REQUEST */
|
|
pins = "gpio86";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio86";
|
|
drive-strength = <2>; /* 2 MA */
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
|
|
qupv3_se2_i2c_active: qupv3_se2_i2c_active {
|
|
mux {
|
|
pins = "gpio6", "gpio7";
|
|
function = "qup2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
|
|
mux {
|
|
pins = "gpio6", "gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_pins: qupv3_se0_spi_pins {
|
|
qupv3_se0_spi_active: qupv3_se0_spi_active {
|
|
mux {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
function = "qup0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
|
|
mux {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0", "gpio1",
|
|
"gpio2", "gpio3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_pins: qupv3_se1_spi_pins {
|
|
qupv3_se1_spi_active: qupv3_se1_spi_active {
|
|
mux {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio69", "gpio70";
|
|
function = "qup1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio69", "gpio70";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
|
|
mux {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio69", "gpio70";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4", "gpio5",
|
|
"gpio69", "gpio70";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_pins: qupv3_se2_spi_pins {
|
|
qupv3_se2_spi_active: qupv3_se2_spi_active {
|
|
mux {
|
|
pins = "gpio6", "gpio7",
|
|
"gpio71", "gpio80";
|
|
function = "qup2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7",
|
|
"gpio71", "gpio80";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
|
|
mux {
|
|
pins = "gpio6", "gpio7",
|
|
"gpio71", "gpio80";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6", "gpio7",
|
|
"gpio71", "gpio80";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_pins: qupv3_se5_spi_pins {
|
|
qupv3_se5_spi_active: qupv3_se5_spi_active {
|
|
mux {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
function = "qup5";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
|
|
mux {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
cci0_suspend: cci0_suspend {
|
|
mux {
|
|
/* CLK, DATA*/
|
|
pins = "gpio23", "gpio22";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23", "gpio22";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci0_active: cci0_active {
|
|
mux {
|
|
/* CLK, DATA*/
|
|
pins = "gpio23", "gpio22";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23", "gpio22";
|
|
bias-pull-up; /* PULL UP*/
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci1_suspend: cci1_suspend {
|
|
mux {
|
|
/* CLK, DATA*/
|
|
pins = "gpio30", "gpio29";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio30", "gpio29";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cci1_active: cci1_active {
|
|
mux {
|
|
/* CLK, DATA*/
|
|
pins = "gpio30", "gpio29";
|
|
function = "cci_i2c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio30", "gpio29";
|
|
bias-pull-up; /* PULL UP*/
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
|
|
/* MCLK 0*/
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
|
|
/* MCLK 0*/
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_active: cam_sensor_mclk1_active {
|
|
/* MCLK 1*/
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
|
|
/* MCLK 1*/
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_active: cam_sensor_mclk2_active {
|
|
/* MCLK 2*/
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
|
|
/* MCLK 2*/
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_active: cam_sensor_mclk3_active {
|
|
/* MCLK 3*/
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
|
|
/* MCLK 3*/
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "cam_mclk";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active {
|
|
/* RESET0 */
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend {
|
|
/* RESET0 */
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active {
|
|
/* RESET1 */
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend {
|
|
/* RESET1 */
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear2_reset_active: cam_sensor_rear2_reset_active {
|
|
/* RESET2 */
|
|
mux {
|
|
pins = "gpio65";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio65";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_rear2_reset_suspend: cam_sensor_rear2_reset_suspend {
|
|
/* RESET2 */
|
|
mux {
|
|
pins = "gpio65";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio65";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_front0_reset_active: cam_sensor_front0_reset_active {
|
|
/* RESET0 */
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend {
|
|
/* RESET0 */
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active {
|
|
/*CSIMUX_OE*/
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend {
|
|
/* CSIMUX_OE */
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active {
|
|
/*CSIMUX_SEL*/
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
bias-disable; /* No PULL */
|
|
drive-strength = <2>; /* 2 MA */
|
|
};
|
|
};
|
|
|
|
cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend {
|
|
/* CSIMUX_SEL */
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
bias-pull-down; /* PULL DOWN */
|
|
drive-strength = <2>; /* 2 MA */
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
pmx_sde: pmx_sde {
|
|
sde_dsi_active: sde_dsi_active {
|
|
mux {
|
|
pins = "gpio82";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio82";
|
|
drive-strength = <8>;
|
|
bias-disable = <0>;
|
|
};
|
|
};
|
|
|
|
sde_dsi_suspend: sde_dsi_suspend {
|
|
mux {
|
|
pins = "gpio82";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio82";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_sde_te {
|
|
sde_te_active: sde_te_active {
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sde_te_suspend: sde_te_suspend {
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "mdp_vsync";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_active {
|
|
ts_int_active: ts_int_active {
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_suspend {
|
|
ts_int_suspend: ts_int_suspend {
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_active {
|
|
ts_reset_active: ts_reset_active {
|
|
mux {
|
|
pins = "gpio71";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio71";
|
|
drive-strength = <8>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_suspend {
|
|
ts_reset_suspend: ts_reset_suspend {
|
|
mux {
|
|
pins = "gpio71";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio71";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_release {
|
|
ts_release: ts_release {
|
|
mux {
|
|
pins = "gpio80", "gpio71";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80", "gpio71";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pm8008_active: pm8008_active {
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
bias-pull-up;
|
|
output-high;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
pm8008_interrupt: pm8008_interrupt {
|
|
mux {
|
|
pins = "gpio25";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio25";
|
|
bias-disable;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
};
|