Ashish Kori
bcd2516842
Enable SMMU stage 1 in fastmap mode for QUPv3 drivers. Change-Id: Ia6c38f6ba97b971d89b1c465fd46525aa4741c4b
604 lines
18 KiB
Devicetree
604 lines
18 KiB
Devicetree
#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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/* QUPv3 North Instances
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* North 0 : SE 0
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* North 1 : SE 1
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* North 2 : SE 2
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* North 4 : SE 4
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* North 5 : SE 5
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*/
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x8c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
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<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
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iommus = <&apps_smmu 0x4e3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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/* Debug UART Instance for RUMI platform */
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qupv3_se2_2uart: qcom,qup_uart@888000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_2uart_active>;
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pinctrl-1 = <&qupv3_se2_2uart_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* 4-wire UART */
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qupv3_se5_4uart: qcom,qup_uart@894000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x894000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
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<&qupv3_se5_tx>;
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pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
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<&qupv3_se5_tx>;
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interrupts-extended = <&intc GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 41 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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/* QUPV3_0_SE0 */
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i3c0: i3c-master@880000 {
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compatible = "qcom,geni-i3c";
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reg = <0x880000 0x4000>,
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<0xec30000 0x10000>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i3c_active>;
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pinctrl-1 = <&qupv3_se0_i3c_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <0>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* I2C */
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se1_i2c: i2c@884000 {
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compatible = "qcom,i2c-geni";
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reg = <0x884000 0x4000>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 1 3 64 0>,
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<&gpi_dma0 1 1 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_i2c_active>;
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pinctrl-1 = <&qupv3_se1_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se4_i2c: i2c@890000 {
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compatible = "qcom,i2c-geni";
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reg = <0x890000 0x4000>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_i2c_active>;
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pinctrl-1 = <&qupv3_se4_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se5_i2c: i2c@894000 {
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compatible = "qcom,i2c-geni";
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reg = <0x894000 0x4000>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 5 3 64 0>,
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<&gpi_dma0 1 5 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_i2c_active>;
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pinctrl-1 = <&qupv3_se5_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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/* SPI */
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_spi: spi@884000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x884000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se1_spi_active>;
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pinctrl-1 = <&qupv3_se1_spi_sleep>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 1 1 64 0>,
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<&gpi_dma0 1 1 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se2_spi: spi@888000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se4_spi: spi@890000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x890000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se4_spi_active>;
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pinctrl-1 = <&qupv3_se4_spi_sleep>;
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se5_spi: spi@894000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x894000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se5_spi_active>;
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pinctrl-1 = <&qupv3_se5_spi_sleep>;
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 5 1 64 0>,
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<&gpi_dma0 1 5 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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/* QUPv3 South_1 Instances
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* South_1 0 : SE 6
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* South_1 1 : SE 7
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* South_1 2 : SE 8
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* South_1 3 : SE 9
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* South_1 4 : SE 10
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* South_1 5 : SE 11
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*/
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qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
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<MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
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iommus = <&apps_smmu 0x023 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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/* 2-wire UART */
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qupv3_se8_2uart: qcom,qup_uart@988000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x988000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_2uart_active>;
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pinctrl-1 = <&qupv3_se8_2uart_sleep>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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/* QUPV3_1_SE0 */
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i3c1: i3c-master@980000 {
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compatible = "qcom,geni-i3c";
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reg = <0x980000 0x4000>,
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<0xec40000 0x10000>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i3c_active>;
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pinctrl-1 = <&qupv3_se6_i3c_sleep>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <0>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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/* I2C */
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qupv3_se6_i2c: i2c@980000 {
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compatible = "qcom,i2c-geni";
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reg = <0x980000 0x4000>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 0 3 64 0>,
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<&gpi_dma1 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@984000 {
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compatible = "qcom,i2c-geni";
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reg = <0x984000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 1 3 64 0>,
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<&gpi_dma1 1 1 3 64 0>;
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dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se8_i2c: i2c@988000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x988000 0x4000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 2 3 64 0>,
|
|
<&gpi_dma1 1 2 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_i2c: i2c@98c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x98c000 0x4000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 3 3 64 0>,
|
|
<&gpi_dma1 1 3 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se9_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
qcom,shared;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se10_i2c: i2c@990000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x990000 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 4 3 64 0>,
|
|
<&gpi_dma1 1 4 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se10_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_i2c: i2c@994000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x994000 0x4000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
dmas = <&gpi_dma1 0 5 3 64 0>,
|
|
<&gpi_dma1 1 5 3 64 0>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_i2c_active>;
|
|
pinctrl-1 = <&qupv3_se11_i2c_sleep>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI */
|
|
qupv3_se6_spi: spi@980000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x980000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se6_spi_active>;
|
|
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 0 1 64 0>,
|
|
<&gpi_dma1 1 0 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se7_spi: spi@984000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x984000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se7_spi_active>;
|
|
pinctrl-1 = <&qupv3_se7_spi_sleep>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 1 1 64 0>,
|
|
<&gpi_dma1 1 1 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se8_spi: spi@988000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x988000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se8_spi_active>;
|
|
pinctrl-1 = <&qupv3_se8_spi_sleep>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 2 1 64 0>,
|
|
<&gpi_dma1 1 2 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se9_spi: spi@98c000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x98c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se9_spi_active>;
|
|
pinctrl-1 = <&qupv3_se9_spi_sleep>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 3 1 64 0>,
|
|
<&gpi_dma1 1 3 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se10_spi: spi@990000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x990000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se10_spi_active>;
|
|
pinctrl-1 = <&qupv3_se10_spi_sleep>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 4 1 64 0>,
|
|
<&gpi_dma1 1 4 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_se11_spi: spi@994000 {
|
|
compatible = "qcom,spi-geni";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x994000 0x4000>;
|
|
reg-names = "se_phys";
|
|
clock-names = "se-clk", "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&qupv3_se11_spi_active>;
|
|
pinctrl-1 = <&qupv3_se11_spi_sleep>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
spi-max-frequency = <50000000>;
|
|
qcom,wrapper-core = <&qupv3_1>;
|
|
dmas = <&gpi_dma1 0 5 1 64 0>,
|
|
<&gpi_dma1 1 5 1 64 0>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
};
|