Puneeth Prabhu
317a01ab27
Add support for mi2s and tdm selection options for core vote and clk attributes. Configure tdm slots from dtsi. Disable wcn-bt for kona. Change-Id: Ieb13c9d0a6c8633a0792769711d00ea825be0a27
383 lines
12 KiB
Devicetree
383 lines
12 KiB
Devicetree
#include "kona-lpi-ar.dtsi"
|
|
#include "kona-va-bolero-ar.dtsi"
|
|
|
|
&bolero_ar {
|
|
qcom,num-macros = <4>;
|
|
bolero-clk-rsc-mngr-ar {
|
|
compatible = "qcom,bolero-clk-rsc-mngr";
|
|
qcom,fs-gen-sequence = <0x3000 0x1>,
|
|
<0x3004 0x1>, <0x3080 0x2>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
|
|
qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
|
|
qcom,va_mclk_mode_muxsel = <0x033A0000>;
|
|
clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
|
|
"wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
|
|
clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
|
|
<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
|
|
<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
|
|
<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
|
|
};
|
|
|
|
tx_macro_ar: tx-macro-ar@3220000 {
|
|
compatible = "qcom,tx-macro";
|
|
reg = <0x3220000 0x0>;
|
|
clock-names = "tx_core_clk", "tx_npl_clk";
|
|
clocks = <&clock_audio_tx_1 0>,
|
|
<&clock_audio_tx_2 0>;
|
|
qcom,tx-swr-gpios = <&tx_swr_gpios_ar>;
|
|
qcom,tx-dmic-sample-rate = <2400000>;
|
|
swr_ar2: tx_swr_master_ar {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote_ar 0>,
|
|
<&lpass_audio_hw_vote_ar 0>;
|
|
qcom,swr-master-version = <0x01050001>;
|
|
qcom,swr_master_id = <3>;
|
|
qcom,mipi-sdw-block-packing-mode = <1>;
|
|
swrm-io-base = <0x3230000 0x0>;
|
|
interrupts-extended =
|
|
<&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
|
qcom,swr-wakeup-required = <1>;
|
|
qcom,swr-num-ports = <5>;
|
|
qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
|
|
<2 ADC1 0x1>, <2 ADC2 0x2>,
|
|
<3 ADC3 0x1>, <3 ADC4 0x2>,
|
|
<4 DMIC0 0x1>, <4 DMIC1 0x2>,
|
|
<4 DMIC2 0x4>, <4 DMIC3 0x8>,
|
|
<5 DMIC4 0x1>, <5 DMIC5 0x2>,
|
|
<5 DMIC6 0x4>, <5 DMIC7 0x8>;
|
|
qcom,swr-num-dev = <1>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
|
wcd938x_tx_slave_ar: wcd938x-tx-slave_ar {
|
|
compatible = "qcom,wcd938x-slave";
|
|
reg = <0x0D 0x01170223>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rx_macro_ar: rx-macro-ar@3200000 {
|
|
compatible = "qcom,rx-macro";
|
|
reg = <0x3200000 0x0>;
|
|
clock-names = "rx_core_clk", "rx_npl_clk";
|
|
clocks = <&clock_audio_rx_1 0>,
|
|
<&clock_audio_rx_2 0>;
|
|
qcom,rx-swr-gpios = <&rx_swr_gpios_ar>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033240D8>;
|
|
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
|
|
qcom,default-clk-id = <TX_CORE_CLK>;
|
|
swr_ar1: rx_swr_master_ar {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote_ar 0>,
|
|
<&lpass_audio_hw_vote_ar 0>;
|
|
qcom,swr-master-version = <0x01050001>;
|
|
qcom,swr_master_id = <2>;
|
|
qcom,mipi-sdw-block-packing-mode = <1>;
|
|
swrm-io-base = <0x3210000 0x0>;
|
|
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <5>;
|
|
qcom,disable-div2-clk-switch = <1>;
|
|
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
|
<1 HPH_R 0x2>, <2 CLSH 0x1>,
|
|
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
|
<4 LO 0x1>, <5 DSD_L 0x1>,
|
|
<5 DSD_R 0x2>;
|
|
qcom,swr-num-dev = <1>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
wcd938x_rx_slave_ar: wcd938x-rx-slave-ar {
|
|
compatible = "qcom,wcd938x-slave";
|
|
reg = <0x0D 0x01170224>;
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa_macro_ar: wsa-macro-ar@3240000 {
|
|
compatible = "qcom,wsa-macro";
|
|
reg = <0x3240000 0x0>;
|
|
clock-names = "wsa_core_clk", "wsa_npl_clk";
|
|
clocks = <&clock_audio_wsa_1 0>,
|
|
<&clock_audio_wsa_2 0>;
|
|
qcom,wsa-swr-gpios = <&wsa_swr_gpios_ar>;
|
|
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
|
|
qcom,default-clk-id = <TX_CORE_CLK>;
|
|
swr_ar0: wsa_swr_master_ar {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote_ar 0>,
|
|
<&lpass_audio_hw_vote_ar 0>;
|
|
qcom,swr-master-version = <0x01050001>;
|
|
qcom,swr_master_id = <1>;
|
|
qcom,mipi-sdw-block-packing-mode = <0>;
|
|
swrm-io-base = <0x3250000 0x0>;
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <8>;
|
|
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
|
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
|
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
|
<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
|
|
<8 SPKR_R_VI 0x3>;
|
|
qcom,swr-num-dev = <2>;
|
|
wsa881x_0211_ar: wsa881x_ar@20170211 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x10 0x20170211>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
|
|
qcom,bolero-handle = <&bolero_ar>;
|
|
};
|
|
|
|
wsa881x_0212_ar: wsa881x_ar@20170212 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x10 0x20170212>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
|
|
qcom,bolero-handle = <&bolero_ar>;
|
|
};
|
|
|
|
wsa881x_0213_ar: wsa881x_ar@21170213 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x10 0x21170213>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
|
|
qcom,bolero-handle = <&bolero_ar>;
|
|
};
|
|
|
|
wsa881x_0214_ar: wsa881x_ar@21170214 {
|
|
compatible = "qcom,wsa881x";
|
|
reg = <0x10 0x21170214>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
|
|
qcom,bolero-handle = <&bolero_ar>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
wcd938x_codec_ar: wcd938x-codec-ar {
|
|
compatible = "qcom,wcd938x-codec";
|
|
qcom,split-codec = <1>;
|
|
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
|
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
|
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
|
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
|
<4 DSD_R 0x2 0 DSD_R>;
|
|
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
|
|
<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
|
|
<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
|
|
<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
|
|
<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
|
|
<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
|
|
<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
|
|
qcom,rx-slave = <&wcd938x_rx_slave_ar>;
|
|
qcom,tx-slave = <&wcd938x_tx_slave_ar>;
|
|
|
|
cdc-vdd-rxtx-supply = <&S4A>;
|
|
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rxtx-current = <30000>;
|
|
|
|
cdc-vddio-supply = <&S4A>;
|
|
qcom,cdc-vddio-voltage = <1800000 1800000>;
|
|
qcom,cdc-vddio-current = <30000>;
|
|
|
|
cdc-vdd-buck-supply = <&S4A>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <650000>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
|
|
qcom,cdc-vdd-mic-bias-current = <30000>;
|
|
|
|
qcom,cdc-micbias1-mv = <1800>;
|
|
qcom,cdc-micbias2-mv = <1800>;
|
|
qcom,cdc-micbias3-mv = <1800>;
|
|
qcom,cdc-micbias4-mv = <1800>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
|
"cdc-vddio",
|
|
"cdc-vdd-buck",
|
|
"cdc-vdd-mic-bias";
|
|
};
|
|
|
|
};
|
|
|
|
&kona_snd_ar {
|
|
qcom,model = "kona-mtp-snd-card";
|
|
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
|
|
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
|
|
qcom,wcn-bt = <0>;
|
|
qcom,ext-disp-audio-rx = <1>;
|
|
qcom,tdm-max-slots = <8>;
|
|
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
|
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
|
qcom,audio-routing =
|
|
"AMIC1", "MIC BIAS1",
|
|
"MIC BIAS1", "Analog Mic1",
|
|
"AMIC2", "MIC BIAS2",
|
|
"MIC BIAS2", "Analog Mic2",
|
|
"AMIC3", "MIC BIAS3",
|
|
"MIC BIAS3", "Analog Mic3",
|
|
"AMIC4", "MIC BIAS3",
|
|
"MIC BIAS3", "Analog Mic4",
|
|
"AMIC5", "MIC BIAS4",
|
|
"MIC BIAS4", "Analog Mic5",
|
|
"TX DMIC0", "MIC BIAS3",
|
|
"MIC BIAS3", "Digital Mic0",
|
|
"TX DMIC1", "MIC BIAS3",
|
|
"MIC BIAS3", "Digital Mic1",
|
|
"TX DMIC2", "MIC BIAS1",
|
|
"MIC BIAS1", "Digital Mic2",
|
|
"TX DMIC3", "MIC BIAS1",
|
|
"MIC BIAS1", "Digital Mic3",
|
|
"TX DMIC4", "MIC BIAS4",
|
|
"MIC BIAS4", "Digital Mic4",
|
|
"TX DMIC5", "MIC BIAS4",
|
|
"MIC BIAS4", "Digital Mic5",
|
|
"IN1_HPHL", "HPHL_OUT",
|
|
"IN2_HPHR", "HPHR_OUT",
|
|
"IN3_AUX", "AUX_OUT",
|
|
"TX SWR_ADC0", "ADC1_OUTPUT",
|
|
"TX SWR_ADC1", "ADC2_OUTPUT",
|
|
"TX SWR_ADC2", "ADC3_OUTPUT",
|
|
"TX SWR_ADC3", "ADC4_OUTPUT",
|
|
"TX SWR_DMIC0", "DMIC1_OUTPUT",
|
|
"TX SWR_DMIC1", "DMIC2_OUTPUT",
|
|
"TX SWR_DMIC2", "DMIC3_OUTPUT",
|
|
"TX SWR_DMIC3", "DMIC4_OUTPUT",
|
|
"TX SWR_DMIC4", "DMIC5_OUTPUT",
|
|
"TX SWR_DMIC5", "DMIC6_OUTPUT",
|
|
"TX SWR_DMIC6", "DMIC7_OUTPUT",
|
|
"TX SWR_DMIC7", "DMIC8_OUTPUT",
|
|
"WSA SRC0_INP", "SRC0",
|
|
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
|
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
|
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
|
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
|
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
|
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
|
"SpkrLeft IN", "WSA_SPK1 OUT",
|
|
"SpkrRight IN", "WSA_SPK2 OUT",
|
|
"VA_AIF1 CAP", "VA_SWR_CLK",
|
|
"VA_AIF2 CAP", "VA_SWR_CLK",
|
|
"VA_AIF3 CAP", "VA_SWR_CLK",
|
|
"VA MIC BIAS3", "Digital Mic0",
|
|
"VA MIC BIAS3", "Digital Mic1",
|
|
"VA MIC BIAS1", "Digital Mic2",
|
|
"VA MIC BIAS1", "Digital Mic3",
|
|
"VA MIC BIAS4", "Digital Mic4",
|
|
"VA MIC BIAS4", "Digital Mic5",
|
|
"VA DMIC0", "VA MIC BIAS3",
|
|
"VA DMIC1", "VA MIC BIAS3",
|
|
"VA DMIC2", "VA MIC BIAS1",
|
|
"VA DMIC3", "VA MIC BIAS1",
|
|
"VA DMIC4", "VA MIC BIAS4",
|
|
"VA DMIC5", "VA MIC BIAS4",
|
|
"VA SWR_ADC0", "VA_SWR_CLK",
|
|
"VA SWR_ADC1", "VA_SWR_CLK",
|
|
"VA SWR_ADC2", "VA_SWR_CLK",
|
|
"VA SWR_ADC3", "VA_SWR_CLK",
|
|
"VA SWR_MIC0", "VA_SWR_CLK",
|
|
"VA SWR_MIC1", "VA_SWR_CLK",
|
|
"VA SWR_MIC2", "VA_SWR_CLK",
|
|
"VA SWR_MIC3", "VA_SWR_CLK",
|
|
"VA SWR_MIC4", "VA_SWR_CLK",
|
|
"VA SWR_MIC5", "VA_SWR_CLK",
|
|
"VA SWR_MIC6", "VA_SWR_CLK",
|
|
"VA SWR_MIC7", "VA_SWR_CLK",
|
|
"VA SWR_ADC0", "ADC1_OUTPUT",
|
|
"VA SWR_ADC1", "ADC2_OUTPUT",
|
|
"VA SWR_ADC2", "ADC3_OUTPUT",
|
|
"VA SWR_ADC3", "ADC4_OUTPUT",
|
|
"VA SWR_MIC0", "DMIC1_OUTPUT",
|
|
"VA SWR_MIC1", "DMIC2_OUTPUT",
|
|
"VA SWR_MIC2", "DMIC3_OUTPUT",
|
|
"VA SWR_MIC3", "DMIC4_OUTPUT",
|
|
"VA SWR_MIC4", "DMIC5_OUTPUT",
|
|
"VA SWR_MIC5", "DMIC6_OUTPUT",
|
|
"VA SWR_MIC6", "DMIC7_OUTPUT",
|
|
"VA SWR_MIC7", "DMIC8_OUTPUT";
|
|
qcom,msm-mbhc-hphl-swh = <1>;
|
|
qcom,msm-mbhc-gnd-swh = <1>;
|
|
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios_ar>;
|
|
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios_ar>;
|
|
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios_ar>;
|
|
asoc-codec = <&stub_codec>, <&bolero_ar>, <&ext_disp_audio_codec>;
|
|
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
|
|
"msm-ext-disp-audio-codec-rx";
|
|
qcom,wsa-max-devs = <2>;
|
|
qcom,wsa-devs = <&wsa881x_0211_ar>, <&wsa881x_0212_ar>,
|
|
<&wsa881x_0213_ar>, <&wsa881x_0214_ar>;
|
|
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
|
|
"SpkrLeft", "SpkrRight";
|
|
qcom,codec-max-aux-devs = <1>;
|
|
qcom,codec-aux-devs = <&wcd938x_codec_ar>;
|
|
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm_ar>,
|
|
<&bolero_ar>;
|
|
};
|
|
|
|
&spf_core_platform {
|
|
cdc_dmic01_gpios_ar: cdc_dmic01_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic01_clk_active_ar &cdc_dmic01_data_active_ar>;
|
|
pinctrl-1 = <&cdc_dmic01_clk_sleep_ar &cdc_dmic01_data_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
cdc_dmic23_gpios_ar: cdc_dmic23_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic23_clk_active_ar &cdc_dmic23_data_active_ar>;
|
|
pinctrl-1 = <&cdc_dmic23_clk_sleep_ar &cdc_dmic23_data_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
cdc_dmic45_gpios_ar: cdc_dmic45_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic45_clk_active_ar &cdc_dmic45_data_active_ar>;
|
|
pinctrl-1 = <&cdc_dmic45_clk_sleep_ar &cdc_dmic45_data_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <158>;
|
|
};
|
|
|
|
wsa_swr_gpios_ar: wsa_swr_clk_data_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wsa_swr_clk_active_ar &wsa_swr_data_active_ar>;
|
|
pinctrl-1 = <&wsa_swr_clk_sleep_ar &wsa_swr_data_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
rx_swr_gpios_ar: rx_swr_clk_data_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&rx_swr_clk_active_ar &rx_swr_data_active_ar
|
|
&rx_swr_data1_active_ar>;
|
|
pinctrl-1 = <&rx_swr_clk_sleep_ar &rx_swr_data_sleep_ar
|
|
&rx_swr_data1_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
tx_swr_gpios_ar: tx_swr_clk_data_pinctrl_ar {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&tx_swr_clk_active_ar &tx_swr_data1_active_ar
|
|
&tx_swr_data2_active_ar>;
|
|
pinctrl-1 = <&tx_swr_clk_sleep_ar &tx_swr_data1_sleep_ar
|
|
&tx_swr_data2_sleep_ar>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <147>;
|
|
};
|
|
};
|