154 lines
3.0 KiB
Devicetree
154 lines
3.0 KiB
Devicetree
&soc {
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timer {
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clock-frequency = <500000>;
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};
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timer@17c20000 {
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clock-frequency = <500000>;
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};
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usb_emu_phy: usb_emu_phy@a720000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x0a720000 0x9500>,
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<0x0a6f8800 0x100>;
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reg-names = "base", "qscratch_base";
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qcom,emu-init-seq = <0xfff0 0x4
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0xfff3 0x4
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0x40 0x4
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0xfff3 0x4
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0xfff0 0x4
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0x100000 0x20
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0x0 0x20
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0x1a0 0x20
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0x100000 0x3c
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0x0 0x3c
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0x10060 0x3c
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0x0 0x4>;
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};
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bi_tcxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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bi_tcxo_ao: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qrbtc-sdm845";
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vdda-phy-supply = <&L18A>;
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vdda-pll-supply = <&L22A>;
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vdda-phy-max-microamp = <62900>;
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vdda-pll-max-microamp = <18300>;
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status = "ok"
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};
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&ufshc_mem {
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limit-tx-hs-gear = <1>;
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limit-rx-hs-gear = <1>;
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scsi-cmd-timeout = <300000>;
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&L7E>;
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vccq2-supply = <&L12A>;
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vcc-max-microamp = <800000>;
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vccq2-max-microamp = <800000>;
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qcom,vddp-ref-clk-supply = <&L22A>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,disable-lpm;
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status = "ok"
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};
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&wdog {
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status = "disabled";
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};
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&usb0 {
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/delete-property/ extcon;
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dwc3@a600000 {
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usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
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maximum-speed = "high-speed";
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};
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};
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&rpmhcc {
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compatible = "qcom,dummycc";
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clock-output-names = "rpmh_clocks";
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};
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&aopcc {
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compatible = "qcom,dummycc";
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clock-output-names = "qdss_clocks";
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};
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&sdhc_1 {
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vdd-supply = <&L7E>;
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qcom,vdd-voltage-level = <2960000 2960000>;
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qcom,vdd-current-level = <0 570000>;
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vdd-io-supply = <&L12A>;
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qcom,vdd-io-always-on;
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qcom,vdd-io-lpm-sup;
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qcom,vdd-io-voltage-level = <1800000 1800000>;
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qcom,vdd-io-current-level = <0 325000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
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&sdc1_rclk_on>;
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pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
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&sdc1_rclk_off>;
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qcom,clk-rates = <400000 25000000 50000000>;
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qcom,bus-speed-mode = "DDR_1p8v";
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/delete-property/qcom,devfreq,freq-table;
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status = "ok"
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};
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&sdhc_2 {
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vdd-supply = <&L9E>;
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qcom,vdd-voltage-level = <2960000 2960000>;
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qcom,vdd-current-level = <0 800000>;
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vdd-io-supply = <&L6E>;
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qcom,vdd-io-voltage-level = <1800000 2950000>;
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qcom,vdd-io-current-level = <0 22000>;
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pinctrl-names = "active", "sleep";
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pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
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qcom,clk-rates = <400000 25000000 50000000>;
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qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
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/delete-property/qcom,devfreq,freq-table;
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status = "ok"
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};
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&qupv3_se10_i2c {
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status = "disabled";
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};
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/* Debug UART Console */
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&qupv3_se9_2uart {
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qcom,rumi_platform;
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};
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