Prakash Gupta
87eb18b764
Remove regulator details for RT and NRT TBUs for scuba. These TBUs are not
power collapsible and hence no need for regulator vote before accessing
tbu registers.
Change-Id: Ia25bbdae756d5fd663684f1348e3f0bc94934b43
Fixes: 174dcab0b1 ("ARM: dts: msm: add bus scaling & gdsc info for scuba apps smmu")
222 lines
7.2 KiB
Devicetree
222 lines
7.2 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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kgsl_smmu: kgsl-smmu@0x59a0000 {
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status = "okay";
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compatible = "qcom,qsmmu-v500";
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reg = <0x59a0000 0x10000>,
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<0x59c2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,no-dynamic-asid;
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qcom,use-3-lvl-tables;
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#global-interrupts = <1>;
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qcom,regulator-names = "vdd";
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vdd-supply = <&gpu_cx_gdsc>;
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
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<&gpucc GPU_CC_AHB_CLK>,
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<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
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clock-names = "gcc_gpu_memnoc_gfx",
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"gcc_gpu_snoc_dvm_gfx",
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"gpu_cc_ahb",
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"gpu_cc_hlos1_vote_gpu_smmu_clk";
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#size-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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qcom,actlr =
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/* ALL CBs of GFX: +15 deep PF */
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<0x0 0x3ff 0x30B>;
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gfx_0_tbu: gfx_0_tbu@0x59c5000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0x59c5000 0x1000>,
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<0x59c2200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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apps_smmu: apps-smmu@0xc600000 {
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status = "okay";
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compatible = "qcom,qsmmu-v500";
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reg = <0xc600000 0x80000>,
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<0xc782000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,skip-init;
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qcom,use-3-lvl-tables;
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#global-interrupts = <1>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
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qcom,msm-bus,name = "apps_smmu";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>;
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qcom,actlr =
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/* For rt TBU +3 deep PF */
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<0x400 0x3ff 0x103>,
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/* For nrt TBU +3 deep PF */
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<0x800 0x3ff 0x103>;
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anoc_1_tbu: anoc_1_tbu@0xc785000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc785000 0x1000>,
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<0xc782200 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x0 0x400>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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qcom,msm-bus,name = "apps_smmu";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 1000>;
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};
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mm_rt_tbu: mm_rt_tbu@0xc789000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc789000 0x1000>,
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<0xc782208 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x400 0x400>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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qcom,msm-bus,name = "apps_smmu";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
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<MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
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<MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 1000>;
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};
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mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
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compatible = "qcom,qsmmuv500-tbu";
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reg = <0xc78d000 0x1000>,
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<0xc782210 0x8>;
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reg-names = "base", "status-reg";
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qcom,stream-id-range = <0x800 0x400>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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qcom,msm-bus,name = "apps_smmu";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
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<MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 0>,
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<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
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<MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 1000>;
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};
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};
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kgsl_iommu_test_device {
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compatible = "iommu-debug-test";
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qcom,iommu-dma = "disabled";
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iommus = <&kgsl_smmu 0x7 0x0>;
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};
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apps_iommu_test_device {
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compatible = "iommu-debug-test";
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qcom,iommu-dma = "disabled";
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iommus = <&apps_smmu 0x1E0 0x0>;
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};
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apps_iommu_coherent_test_device {
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compatible = "iommu-debug-test";
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qcom,iommu-dma = "disabled";
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iommus = <&apps_smmu 0x1E1 0x0>;
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dma-coherent;
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};
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};
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