Swetha Chikkaboraiah
7babdba8ba
Add initial device tree support for SDM429/439/QM215 target.
This is a snapshot of dtsi files as of msm-4.9
'commit <033db782f19bcc5b961fcb676404466c2c07d0f8>
("msm: kgsl: Protect the memdesc->gpuaddr in SVM use cases")'.
Snapshot of msm-pm8916.dtsi is taken from msm-3.10 And
renamed to pm8916.dtsi to be comaptible with 4.19 kernel
'commit <795bad7cbc25468d9b0dc7c011cc7ef2e3f4c0b2>
power: qpnp-linear-charger: fix mutex lockup")'.
Change-Id: Id25960963b2ffc8bbb23abb6a802d146bb643d02
133 lines
2.3 KiB
Devicetree
133 lines
2.3 KiB
Devicetree
/ {
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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};
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cluster1 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_101: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_101: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_102: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_102: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_0>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L1_I_103: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_103: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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};
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energy_costs: energy-costs {
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CPU_COST_0: core-cost0 {
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busy-cost-data = <
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656 159
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682 172
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748 207
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827 244
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853 256
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893 283
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958 327
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1024 343
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>;
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};
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};
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};
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