Sankeerth Billakanti
97b0834063
The dp-usb3 combo phy power is controlled by the QLINK ARC. If QLINK ARC is not enabled, the ref_clk for the phy is powered-down. This was causing the DP pll to not lock sometimes and causing display blankout or flickers. This change will vote for the QLINK ARC to power the ref clk for the dp-usb3 combo phy. Change-Id: I2a70e5a197096dcc0330541c761130afa2e7e4ee
45 lines
1.1 KiB
Devicetree
45 lines
1.1 KiB
Devicetree
&soc {
|
|
mdss_dsi0_pll: qcom,mdss_dsi0_pll {
|
|
compatible = "qcom,mdss_dsi_pll_10nm";
|
|
label = "MDSS DSI 0 PLL";
|
|
cell-index = <0>;
|
|
#clock-cells = <1>;
|
|
reg = <0xae94a00 0x1e0>,
|
|
<0xae94400 0x800>,
|
|
<0xaf03000 0x8>,
|
|
<0xae94200 0x100>;
|
|
reg-names = "pll_base", "phy_base", "gdsc_base",
|
|
"dynamic_pll_base";
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
|
|
clock-names = "iface_clk";
|
|
clock-rate = <0>;
|
|
memory-region = <&dfps_data_memory>;
|
|
qcom,dsi-pll-ssc-en;
|
|
qcom,dsi-pll-ssc-mode = "down-spread";
|
|
};
|
|
|
|
mdss_dp_pll: qcom,mdss_dp_pll@ae90000 {
|
|
compatible = "qcom,mdss_dp_pll_10nm";
|
|
label = "MDSS DP PLL";
|
|
cell-index = <0>;
|
|
#clock-cells = <1>;
|
|
|
|
reg = <0x088ea000 0x200>,
|
|
<0x088eaa00 0x200>,
|
|
<0x088ea200 0x200>,
|
|
<0x088ea600 0x200>,
|
|
<0xaf03000 0x8>;
|
|
reg-names = "pll_base", "phy_base", "ln_tx0_base",
|
|
"ln_tx1_base", "gdsc_base";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&rpmhcc RPMH_QLINK_CLK>,
|
|
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "iface_clk", "ref_clk_src", "ref_clk",
|
|
"pipe_clk";
|
|
clock-rate = <0>;
|
|
};
|
|
|
|
};
|