Raviteja
d74de2714f
In certain cases of 120 fps boot up with continuous splash, the default mdp clock set at max svs level is low and is causing underrun till the first commit comes. Increasing the mdp default clock to max nominal level will avoid this scenario. Change-Id: Ic6a04dca6505e741041457a9a455e086523f297d
707 lines
19 KiB
Devicetree
707 lines
19 KiB
Devicetree
#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp {
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compatible = "qcom,sde-kms";
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reg = <0xae00000 0x84208>,
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<0xaeb0000 0x2008>,
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<0xaeac000 0x214>,
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<0xae8f000 0x02c>,
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<0xaf50000 0x038>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"sid_phys",
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"swfuse_phys";
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clocks =
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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clock-rate = <0 0 0 0 460000000 19200000 460000000
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200000000>;
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clock-max-rate = <0 0 0 0 460000000 19200000 460000000
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460000000>;
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>;
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qcom,sde-ctl-size = <0x1dc>;
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qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
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qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary", "primary", "none",
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"none";
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qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000 0x57000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-dest-scaler-top-off = <0x00061000>;
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qcom,sde-dest-scaler-top-size = <0x1c>;
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qcom,sde-dest-scaler-off = <0x800 0x1000>;
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qcom,sde-dest-scaler-size = <0x800>;
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qcom,sde-wb-off = <0x66000>;
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qcom,sde-wb-size = <0x2c8>;
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qcom,sde-wb-xin-id = <6>;
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qcom,sde-wb-id = <2>;
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qcom,sde-wb-clk-ctrl = <0x2bc 16>;
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qcom,sde-intf-off = <0x6b000 0x6b800
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0x6c000 0x6c800>;
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qcom,sde-intf-size = <0x2b8>;
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qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
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qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>;
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qcom,sde-merge-3d-off = <0x84000 0x84100>;
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qcom,sde-merge-3d-size = <0x100>;
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qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>;
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qcom,sde-cdm-off = <0x7a200>;
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qcom,sde-cdm-size = <0x224>;
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qcom,sde-dsc-off = <0x81000 0x81400>;
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qcom,sde-dsc-size = <0x140>;
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qcom,sde-dsc-pair-mask = <2 1>;
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qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
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0x30e0>;
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qcom,sde-dither-version = <0x00010000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "vig",
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"dma", "dma", "dma";
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qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>;
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qcom,sde-sspp-src-size = <0x1f8>;
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qcom,sde-sspp-xin-id = <0 4 1 5 9>;
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qcom,sde-sspp-excl-rect = <1 1 1 1 1>;
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qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <2 1 4 3>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0>;
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qcom,sde-max-per-pipe-bw-kbps = <4700000 4700000
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4700000 4700000
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4700000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <4700000 4700000
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4700000 4700000
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4700000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>,
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<0x2ac 8>, <0x2b4 8>, <0x2c4 8>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-type = "qseedv3lite";
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-mixer-linewidth = <2560>;
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qcom,sde-sspp-linewidth = <2880>;
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qcom,sde-vig-sspp-linewidth = <4096>;
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qcom,sde-wb-linewidth = <4096>;
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qcom,sde-mixer-blendstages = <0x9>;
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qcom,sde-highest-bank-bit = <0x1>;
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qcom,sde-ubwc-version = <0x300>;
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qcom,sde-ubwc-swizzle = <0x6>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-ubwc-static = <0x1>;
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qcom,sde-macrotile-mode = <0x1>;
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qcom,sde-smart-panel-align-mode = <0xc>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-src-split;
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qcom,sde-pipe-order-version = <0x1>;
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qcom,sde-has-dim-layer;
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qcom,sde-has-dest-scaler;
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qcom,sde-has-idle-pc;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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qcom,sde-max-bw-low-kbps = <5800000>;
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qcom,sde-max-bw-high-kbps = <8600000>;
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qcom,sde-min-core-ib-kbps = <4800000>;
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qcom,sde-min-llcc-ib-kbps = <0>;
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qcom,sde-min-dram-ib-kbps = <800000>;
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qcom,sde-dram-channels = <2>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-dspp-ltm-version = <0x00010000>;
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/* offsets are based off dspp 0 and dspp 1 */
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qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x1040>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
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qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
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/* macrotile & macrotile-qseed has the same configs */
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qcom,sde-danger-lut = <0x000000ff 0x0000ffff
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0x00000000 0x00000000 0x0000ffff>;
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qcom,sde-safe-lut-linear = <0 0xfffc>;
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qcom,sde-safe-lut-macrotile = <0 0xff00>;
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/* same as safe-lut-macrotile */
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qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
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qcom,sde-safe-lut-nrt = <0 0xffff>;
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qcom,sde-safe-lut-cwb = <0 0x3ff>;
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/* creq LUTs */
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qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>;
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qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
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qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
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qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
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qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0>;
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qcom,sde-reg-dma-version = <0x00010002>;
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qcom,sde-reg-dma-trigger-off = <0x119c>;
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qcom,sde-reg-dma-xin-id = <7>;
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qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
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qcom,sde-secure-sid-mask = <0xb41 0xf41>;
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qcom,sde-sspp-vig-blocks {
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xa0>;
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qcom,sde-vig-gamut = <0x1d00 0x00060000>;
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qcom,sde-vig-igc = <0x1d00 0x00060000>;
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qcom,sde-vig-inverse-pma;
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};
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qcom,sde-sspp-dma-blocks {
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dgm@0 {
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qcom,sde-dma-igc = <0x400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x200>;
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};
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dgm@1 {
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qcom,sde-dma-igc = <0x1400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x1200>;
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};
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x0 0x00030001>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone= <0x900 0x00010007>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-gamut = <0x1000 0x00040002>;
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qcom,sde-dspp-pcc = <0x1700 0x00040000>;
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qcom,sde-dspp-gc = <0x17c0 0x00010008>;
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0xb40 0x402>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0xb41 0x0>,
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<&apps_smmu 0xf41 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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/* data and reg bus scale settings */
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qcom,sde-data-bus {
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qcom,msm-bus,name = "mdss_sde";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>, <23 512 0 0>,
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<22 512 0 6400000>, <23 512 0 6400000>,
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<22 512 0 6400000>, <23 512 0 6400000>;
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};
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qcom,sde-reg-bus {
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qcom,msm-bus,name = "mdss_reg";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 590 0 0>,
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<1 590 0 76800>,
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<1 590 0 150000>,
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<1 590 0 300000>;
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};
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qcom,sde-limits {
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qcom,sde-linewidth-limits {
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qcom,sde-limit-name = "sspp_linewidth_usecases";
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qcom,sde-limit-cases = "vig", "dma", "scale", "inline_rot";
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qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>;
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qcom,sde-limit-values = <0x1 4096>,
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<0x5 2560>,
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<0x2 2880>,
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<0x9 1088>;
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};
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qcom,sde-bw-limits {
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qcom,sde-limit-name = "sde_bwlimit_usecases";
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qcom,sde-limit-cases = "per_vig_pipe",
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"per_dma_pipe",
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"total_max_bw",
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"camera_concurrency",
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"cwb_concurrency";
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qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>;
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qcom,sde-limit-values = <0x1 4700000>,
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<0x11 4700000>,
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<0x9 4700000>,
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<0x19 4700000>,
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<0x2 4700000>,
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<0x12 4700000>,
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<0xa 4700000>,
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<0x1a 4700000>,
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<0x4 8600000>,
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<0x14 8600000>,
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<0xc 5800000>,
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<0x1c 5800000>;
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};
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};
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};
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sde_rscc: qcom,sde_rscc {
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cell-index = <0>;
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compatible = "qcom,sde-rsc";
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reg = <0xaf20000 0x3c50>,
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<0xaf30000 0x3fd4>;
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reg-names = "drv", "wrapper";
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qcom,sde-rsc-version = <3>;
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qcom,sde-dram-channels = <2>;
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vdd-supply = <&mdss_core_gdsc>;
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clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
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/* data and reg bus scale settings */
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qcom,sde-data-bus {
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qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<20003 20513 0 0>, <20004 20513 0 0>,
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<20003 20513 0 6400000>, <20004 20513 0 6400000>,
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<20003 20513 0 6400000>, <20004 20513 0 6400000>;
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};
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qcom,sde-ebi-bus {
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qcom,msm-bus,name = "disp_rsc_ebi";
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qcom,msm-bus,active-only;
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<20000 20512 0 0>,
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<20000 20512 0 6400000>,
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<20000 20512 0 6400000>;
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};
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qcom,sde-reg-bus {
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qcom,msm-bus,name = "disp_rsc_reg";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 590 0 0>,
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<1 590 0 76800>,
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<1 590 0 150000>,
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<1 590 0 300000>;
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};
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};
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mdss_rotator: qcom,mdss_rotator {
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status = "disabled";
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compatible = "qcom,sde_rotator";
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reg = <0xae00000 0xac000>,
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<0xaeb8000 0x3000>;
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reg-names = "mdp_phys",
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"rot_vbif_phys";
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#list-cells = <1>;
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qcom,mdss-rot-mode = <1>;
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qcom,mdss-highest-bank-bit = <0x3>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_rotator";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<25 512 0 0>,
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<25 512 0 6400000>,
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<25 512 0 6400000>;
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rot-vdd-supply = <&mdss_core_gdsc>;
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qcom,supply-names = "rot-vdd";
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clocks =
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_SF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>;
|
|
clock-names = "gcc_iface", "gcc_bus",
|
|
"iface_clk", "rot_clk";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <2 0>;
|
|
|
|
power-domains = <&mdss_mdp>;
|
|
|
|
/* Offline rotator QoS setting */
|
|
qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
|
|
qcom,mdss-rot-vbif-memtype = <3 3>;
|
|
qcom,mdss-rot-cdp-setting = <1 1>;
|
|
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
|
|
qcom,mdss-rot-danger-lut = <0x0 0x0>;
|
|
qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
|
|
|
|
qcom,mdss-default-ot-rd-limit = <32>;
|
|
qcom,mdss-default-ot-wr-limit = <32>;
|
|
|
|
qcom,mdss-sbuf-headroom = <20>;
|
|
|
|
/* reg bus scale settings */
|
|
rot_reg: qcom,rot-reg-bus {
|
|
qcom,msm-bus,name = "mdss_rot_reg";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 590 0 0>,
|
|
<1 590 0 76800>;
|
|
};
|
|
|
|
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
|
|
compatible = "qcom,smmu_sde_rot_unsec";
|
|
iommus = <&apps_smmu 0x135C 0x0>;
|
|
};
|
|
|
|
smmu_rot_sec: qcom,smmu_rot_sec_cb {
|
|
compatible = "qcom,smmu_sde_rot_sec";
|
|
iommus = <&apps_smmu 0x135d 0x0>;
|
|
};
|
|
};
|
|
|
|
mdss_dsi0: qcom,mdss_dsi0_ctrl {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.4";
|
|
label = "dsi-ctrl-0";
|
|
cell-index = <0>;
|
|
frame-threshold-time-us = <1000>;
|
|
reg = <0xae94000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <4 0>;
|
|
vdda-1p2-supply = <&L9A>;
|
|
refgen-supply = <&refgen>;
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1152000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1: qcom,mdss_dsi1_ctrl {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.4";
|
|
label = "dsi-ctrl-1";
|
|
frame-threshold-time-us = <1000>;
|
|
cell-index = <1>;
|
|
reg = <0xae96000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <5 0>;
|
|
vdda-1p2-supply = <&L9A>;
|
|
refgen-supply = <&refgen>;
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1152000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_dp: qcom,dp_display@ae90000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,dp-display";
|
|
|
|
vdda-1p2-supply = <&L9A>;
|
|
reg = <0xae90000 0x0dc>,
|
|
<0xae90200 0x0c0>,
|
|
<0xae90400 0x508>,
|
|
<0xae91000 0x094>,
|
|
<0x88eaa00 0x198>,
|
|
<0x88ea200 0x150>,
|
|
<0x88ea600 0x150>,
|
|
<0xaf02000 0x2c4>,
|
|
<0x88ea040 0x10>,
|
|
<0x88e8000 0x20>,
|
|
<0x0aee1000 0x2a>,
|
|
<0xae91400 0x095>;
|
|
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
|
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
|
"dp_mmss_cc", "dp_pll",
|
|
"usb3_dp_com", "hdcp_physical", "dp_p1";
|
|
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <12 0>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
|
<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
|
<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
|
|
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
|
clock-names = "core_aux_clk", "core_usb_pipe_clk",
|
|
"core_usb_ref_clk_src",
|
|
"link_clk", "link_iface_clk",
|
|
"pixel_clk_rcg", "pixel_parent",
|
|
"pixel1_clk_rcg", "pixel1_parent",
|
|
"strm0_pixel_clk", "strm1_pixel_clk";
|
|
|
|
qcom,phy-version = <0x420>;
|
|
qcom,aux-cfg0-settings = [20 00];
|
|
qcom,aux-cfg1-settings = [24 13];
|
|
qcom,aux-cfg2-settings = [28 A4];
|
|
qcom,aux-cfg3-settings = [2c 00];
|
|
qcom,aux-cfg4-settings = [30 0a];
|
|
qcom,aux-cfg5-settings = [34 26];
|
|
qcom,aux-cfg6-settings = [38 0a];
|
|
qcom,aux-cfg7-settings = [3c 03];
|
|
qcom,aux-cfg8-settings = [40 b7];
|
|
qcom,aux-cfg9-settings = [44 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,mst-enable;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1152000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <21800>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
|
|
compatible = "qcom,dsi-phy-v4.1";
|
|
label = "dsi-phy-0";
|
|
cell-index = <0>;
|
|
reg = <0xae94400 0x800>,
|
|
<0xae94200 0x100>;
|
|
reg-names = "dsi_phy", "dyn_refresh_base";
|
|
vdda-0p9-supply = <&L5A>;
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy1: qcom,mdss_dsi_phy1 {
|
|
compatible = "qcom,dsi-phy-v4.1";
|
|
label = "dsi-phy-1";
|
|
cell-index = <1>;
|
|
reg = <0xae96400 0x800>,
|
|
<0xae96200 0x100>;
|
|
reg-names = "dsi_phy", "dyn_refresh_base";
|
|
vdda-0p9-supply = <&L5A>;
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <36000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|