418 lines
11 KiB
Devicetree
418 lines
11 KiB
Devicetree
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp {
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compatible = "qcom,sde-kms";
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reg = <0x5e00000 0x8f030>,
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<0x5eb0000 0x2008>,
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<0x5e8f000 0x02c>,
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<0xc125ba4 0x20>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"sid_phys",
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"sde_imem_phys";
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clocks =
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<&gcc GCC_DISP_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
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"div_clk",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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clock-rate = <0 0 0 0 0 256000000 19200000 192000000 192000000>;
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clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000
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307000000>;
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sde-vdd-supply = <&mdss_core_gdsc>;
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/* interrupt config */
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#power-domain-cells = <0>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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qcom,sde-ctl-off = <0x2000>;
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qcom,sde-ctl-size = <0x1dc>;
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qcom,sde-ctl-display-pref = "primary";
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qcom,sde-mixer-off = <0x45000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000>;
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qcom,sde-dspp-size = <0xfe4>;
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qcom,sde-intf-off = <0x0 0x6b800>;
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qcom,sde-intf-size = <0x2b8>;
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qcom,sde-intf-type = "none", "dsi";
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qcom,sde-pp-off = <0x71000>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-dither-off = <0x30e0>;
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qcom,sde-dither-version = <0x00010000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "dma";
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qcom,sde-sspp-off = <0x5000 0x25000>;
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qcom,sde-sspp-src-size = <0x1f8>;
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qcom,sde-sspp-xin-id = <0 1>;
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qcom,sde-sspp-excl-rect = <1 1>;
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qcom,sde-sspp-smart-dma-priority = <2 1>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <0>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-mixer-stage-base-layer;
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qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl =
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<0x2ac 0>, <0x2ac 8>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-type = "qseedv3lite";
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-mixer-linewidth = <2048>;
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qcom,sde-sspp-linewidth = <2160>;
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qcom,sde-mixer-blendstages = <0x4>;
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qcom,sde-highest-bank-bit = <0x1>;
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qcom,sde-ubwc-version = <0x100>;
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qcom,sde-ubwc-swizzle = <0x7>;
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qcom,sde-ubwc-static = <0x11F>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-dim-layer;
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qcom,sde-has-idle-pc;
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qcom,sde-max-bw-low-kbps = <3100000>;
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qcom,sde-max-bw-high-kbps = <4000000>;
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qcom,sde-min-core-ib-kbps = <2400000>;
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qcom,sde-min-llcc-ib-kbps = <800000>;
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qcom,sde-min-dram-ib-kbps = <800000>;
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qcom,sde-dram-channels = <1>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x2008>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
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qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
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/*Pending macrotile & macrotile-qseed has the same configs */
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qcom,sde-danger-lut = <0x000000ff 0x0000ffff
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0x00000000 0x00000000 0x0000ffff>;
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qcom,sde-safe-lut-linear = <0 0xfff0>;
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qcom,sde-safe-lut-macrotile = <0 0xff00>;
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/* same as safe-lut-macrotile */
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qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
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qcom,sde-safe-lut-nrt = <0 0xffff>;
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qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
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qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
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qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
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qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-secure-sid-mask = <0x0000421>;
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qcom,sde-num-mnoc-ports = <1>;
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qcom,sde-axi-bus-width = <16>;
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qcom,sde-sspp-vig-blocks {
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xa0>;
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qcom,sde-vig-inverse-pma;
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x0 0x00030001>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone= <0x900 0x00010007>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-pcc = <0x1700 0x00040000>;
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qcom,sde-dspp-gc = <0x17c0 0x00010008>;
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "sde-vdd";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x420 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x421 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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/* data and reg bus scale settings */
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qcom,sde-data-bus {
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qcom,msm-bus,name = "mdss_sde";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>,
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<22 512 0 4800000>,
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<22 512 0 4800000>;
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};
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qcom,sde-reg-bus {
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qcom,msm-bus,name = "mdss_reg";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 590 0 0>,
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<1 590 0 76800>,
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<1 590 0 150000>,
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<1 590 0 300000>;
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};
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qcom,sde-limits {
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qcom,sde-linewidth-limits {
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qcom,sde-limit-name = "sspp_linewidth_usecases";
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qcom,sde-limit-cases = "vig", "dma", "scale";
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qcom,sde-limit-ids= <0x1 0x2 0x4>;
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qcom,sde-limit-values = <0x1 4096>,
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<0x5 2560>,
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<0x2 2160>;
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};
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qcom,sde-bw-limits {
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qcom,sde-limit-name = "sde_bwlimit_usecases";
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qcom,sde-limit-cases = "per_vig_pipe",
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"per_dma_pipe",
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"total_max_bw",
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"camera_concurrency";
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qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
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qcom,sde-limit-values = <0x1 2600000>,
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<0x9 2600000>,
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<0x2 2600000>,
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<0xa 2600000>,
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<0x4 4000000>,
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<0xc 3100000>;
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};
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};
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};
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mdss_rotator: qcom,mdss_rotator {
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compatible = "qcom,sde_rotator";
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reg = <0x5e00000 0xac000>,
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<0x5eb0000 0x2008>;
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reg-names = "mdp_phys",
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"rot_vbif_phys";
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#list-cells = <1>;
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qcom,mdss-rot-mode = <1>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_rotator";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>,
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<22 512 0 6400000>,
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<22 512 0 6400000>;
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rot-vdd-supply = <&mdss_core_gdsc>;
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qcom,supply-names = "rot-vdd";
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clocks =
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<&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface",
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"iface_clk", "rot_clk";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <2 0>;
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power-domains = <&mdss_mdp>;
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/*Offline rotator RT setting */
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qcom,mdss-rot-parent = <&mdss_mdp 0>;
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qcom,mdss-rot-xin-id = <10 11>;
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/* Offline rotator QoS setting */
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qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
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qcom,mdss-rot-cdp-setting = <1 1>;
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qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
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qcom,mdss-rot-danger-lut = <0x0 0x0>;
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qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
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qcom,mdss-default-ot-rd-limit = <32>;
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qcom,mdss-default-ot-wr-limit = <32>;
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qcom,mdss-sbuf-headroom = <20>;
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/* reg bus scale settings */
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rot_reg: qcom,rot-reg-bus {
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qcom,msm-bus,name = "mdss_rot_reg";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 590 0 0>,
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<1 590 0 76800>;
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};
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smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
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compatible = "qcom,smmu_sde_rot_unsec";
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iommus = <&apps_smmu 0x43C 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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};
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smmu_rot_sec: qcom,smmu_rot_sec_cb {
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compatible = "qcom,smmu_sde_rot_sec";
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iommus = <&apps_smmu 0x43D 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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};
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mdss_dsi0: qcom,mdss_dsi0_ctrl {
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compatible = "qcom,dsi-ctrl-hw-v2.4";
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label = "dsi-ctrl-0";
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cell-index = <0>;
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frame-threshold-time-us = <1000>;
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reg = <0x5e94000 0x400>,
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<0x5f08000 0x4>;
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reg-names = "dsi_ctrl", "disp_cc_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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vdda-1p2-supply = <&L18A>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg",
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"esc_clk";
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1232000>;
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qcom,supply-max-voltage = <1232000>;
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qcom,supply-enable-load = <21800>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
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compatible = "qcom,dsi-phy-v2.0";
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label = "dsi-phy-0";
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cell-index = <0>;
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reg = <0x5e94400 0x588>,
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<0x5e01400 0x100>,
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<0x5e94200 0x100>;
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reg-names = "dsi_phy", "phy_clamp_base",
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"dyn_refresh_base";
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vdda-0p9-supply = <&VDD_MX_LEVEL>;
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qcom,platform-strength-ctrl = [ff 06
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ff 06
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ff 06
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ff 06
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ff 00];
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qcom,platform-lane-config = [00 00 10 0f
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00 00 10 0f
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00 00 10 0f
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00 00 10 0f
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00 00 10 8f];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,panel-allow-phy-poweroff;
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage =
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<RPM_SMD_REGULATOR_LEVEL_NOM>;
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qcom,supply-max-voltage =
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<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
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qcom,supply-off-min-voltage =
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<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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};
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