zhouwl
6204f33cd5
This is Awinic official release, the key change is i2c_read function, use i2c_transfer to replace the old one, add thread_lock to protect i2c operation safety, in order to resolve a potential no sound risk after supporting different audio scenarios feature. NO_PROP_NEEDED: aw882xx doesn't use in bq-shm2018 products. Change-Id: I3daeb35c6a349c65bdb723d7f12430634abbf8f2 Signed-off-by: zhouwl <zhouwl@lenovo.com> Reviewed-on: https://gerrit.mot.com/1537490 SLTApproved: Slta Waiver SME-Granted: SME Approvals Granted Tested-by: Jira Key Reviewed-by: Hujun Liao <liaohj@motorola.com> Reviewed-by: Wen Xie <xiewen3@motorola.com> Submit-Approved: Jira Key Reviewed-by: Yunfei Guo <guoyf2@motorola.com>
1569 lines
57 KiB
C
1569 lines
57 KiB
C
#ifndef __AW882XX_REG_H__
|
|
#define __AW882XX_REG_H__
|
|
|
|
/* registers list */
|
|
#define AW882XX_ID_REG (0x00)
|
|
#define AW882XX_SYSST_REG (0x01)
|
|
#define AW882XX_SYSINT_REG (0x02)
|
|
#define AW882XX_SYSINTM_REG (0x03)
|
|
#define AW882XX_SYSCTRL_REG (0x04)
|
|
#define AW882XX_SYSCTRL2_REG (0x05)
|
|
#define AW882XX_I2SCTRL_REG (0x06)
|
|
#define AW882XX_I2SCFG1_REG (0x07)
|
|
#define AW882XX_I2SCFG2_REG (0x08)
|
|
#define AW882XX_HAGCCFG1_REG (0x09)
|
|
#define AW882XX_HAGCCFG2_REG (0x0A)
|
|
#define AW882XX_HAGCCFG3_REG (0x0B)
|
|
#define AW882XX_HAGCCFG4_REG (0x0C)
|
|
#define AW882XX_HAGCCFG5_REG (0x0D)
|
|
#define AW882XX_HAGCCFG6_REG (0x0E)
|
|
#define AW882XX_HAGCCFG7_REG (0x0F)
|
|
#define AW882XX_HAGCST_REG (0x10)
|
|
#define AW882XX_PRODID_REG (0x11)
|
|
#define AW882XX_VBAT_REG (0x12)
|
|
#define AW882XX_TEMP_REG (0x13)
|
|
#define AW882XX_PVDD_REG (0x14)
|
|
#define AW882XX_DBGCTRL_REG (0x20)
|
|
#define AW882XX_I2SINT_REG (0x21)
|
|
#define AW882XX_I2SCAPCNT_REG (0x22)
|
|
#define AW882XX_CRCIN_REG (0x38)
|
|
#define AW882XX_CRCOUT_REG (0x39)
|
|
#define AW882XX_VSNCTRL1_REG (0x50)
|
|
#define AW882XX_ISNCTRL1_REG (0x52)
|
|
#define AW882XX_ISNCTRL2_REG (0x53)
|
|
#define AW882XX_VTMCTRL1_REG (0x54)
|
|
#define AW882XX_VTMCTRL2_REG (0x55)
|
|
#define AW882XX_VTMCTRL3_REG (0x56)
|
|
#define AW882XX_ISNDAT_REG (0x57)
|
|
#define AW882XX_VSNDAT_REG (0x58)
|
|
#define AW882XX_PWMCTRL_REG (0x59)
|
|
#define AW882XX_PWMCTRL2_REG (0x5A)
|
|
#define AW882XX_BSTCTRL1_REG (0x60)
|
|
#define AW882XX_BSTCTRL2_REG (0x61)
|
|
#define AW882XX_BSTCTRL3_REG (0x62)
|
|
#define AW882XX_BSTDBG1_REG (0x63)
|
|
#define AW882XX_BSTDBG2_REG (0x64)
|
|
#define AW882XX_BSTDBG3_REG (0x65)
|
|
#define AW882XX_PLLCTRL1_REG (0x66)
|
|
#define AW882XX_PLLCTRL2_REG (0x67)
|
|
#define AW882XX_PLLCTRL3_REG (0x68)
|
|
#define AW882XX_CDACTRL1_REG (0x69)
|
|
#define AW882XX_CDACTRL2_REG (0x6A)
|
|
#define AW882XX_SADCCTRL_REG (0x6B)
|
|
#define AW882XX_TESTCTRL1_REG (0x70)
|
|
#define AW882XX_TESTCTRL2_REG (0x71)
|
|
#define AW882XX_EFCTRL1_REG (0x72)
|
|
#define AW882XX_EFCTRL2_REG (0x73)
|
|
#define AW882XX_EFWH_REG (0x74)
|
|
#define AW882XX_EFWM2_REG (0x75)
|
|
#define AW882XX_EFWM1_REG (0x76)
|
|
#define AW882XX_EFWL_REG (0x77)
|
|
#define AW882XX_EFRH_REG (0x78)
|
|
#define AW882XX_EFRM2_REG (0x79)
|
|
#define AW882XX_EFRM1_REG (0x7A)
|
|
#define AW882XX_EFRL_REG (0x7B)
|
|
#define AW882XX_TESTDET_REG (0x7C)
|
|
|
|
/********************************************
|
|
* Register Access
|
|
*******************************************/
|
|
#define AW882XX_REG_MAX (0x7D)
|
|
|
|
#define REG_NONE_ACCESS (0)
|
|
#define REG_RD_ACCESS (1 << 0)
|
|
#define REG_WR_ACCESS (1 << 1)
|
|
|
|
const unsigned char aw882xx_reg_access[AW882XX_REG_MAX] = {
|
|
[AW882XX_ID_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_SYSST_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_SYSINT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_SYSINTM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_SYSCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_I2SCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_I2SCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_I2SCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG6_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCCFG7_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_HAGCST_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_PRODID_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_VBAT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_TEMP_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_PVDD_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_DBGCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_I2SINT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_I2SCAPCNT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_CRCIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_CRCOUT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_VSNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_ISNCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_ISNCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_VTMCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_VTMCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_VTMCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_ISNDAT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_VSNDAT_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_PWMCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_PWMCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTDBG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTDBG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_BSTDBG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_PLLCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_PLLCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_PLLCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_CDACTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_CDACTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_SADCCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_TESTCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFWM2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFWM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
|
|
[AW882XX_EFRH_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_EFRM2_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_EFRM1_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_EFRL_REG] = (REG_RD_ACCESS),
|
|
[AW882XX_TESTDET_REG] = (REG_RD_ACCESS),
|
|
};
|
|
|
|
/********************************************
|
|
* Register Detail
|
|
*******************************************/
|
|
/* detail information of registers begin */
|
|
/* ID (0x00) detail */
|
|
/* IDCODE bit 15:0 (ID 0x00) */
|
|
#define AW882XX_IDCODE_START_BIT (0)
|
|
#define AW882XX_IDCODE_BITS_LEN (16)
|
|
#define AW882XX_IDCODE_MASK \
|
|
(~(((1<<AW882XX_IDCODE_BITS_LEN)-1)<<AW882XX_IDCODE_START_BIT))
|
|
|
|
#define AW882XX_IDCODE_DEFAULT_VALUE (0x1852)
|
|
#define AW882XX_IDCODE_DEFAULT \
|
|
(AW882XX_IDCODE_DEFAULT_VALUE<<AW882XX_IDCODE_START_BIT)
|
|
|
|
/* default value of ID (0x00) */
|
|
/* #define AW882XX_ID_DEFAULT (0x1852) */
|
|
|
|
/* SYSST (0x01) detail */
|
|
/* OVP2S bit 15 (SYSST 0x01) */
|
|
#define AW882XX_OVP2S_START_BIT (15)
|
|
#define AW882XX_OVP2S_BITS_LEN (1)
|
|
#define AW882XX_OVP2S_MASK \
|
|
(~(((1<<AW882XX_OVP2S_BITS_LEN)-1)<<AW882XX_OVP2S_START_BIT))
|
|
|
|
#define AW882XX_OVP2S_NONE (0)
|
|
#define AW882XX_OVP2S_NONE_VALUE \
|
|
(AW882XX_OVP2S_NONE << AW882XX_OVP2S_START_BIT)
|
|
#define AW882XX_OVP2S_TRIG (1)
|
|
#define AW882XX_OVP2S_TRIG_VALUE \
|
|
(AW882XX_OVP2S_TRIG << AW882XX_OVP2S_START_BIT)
|
|
|
|
#define AW882XX_OVP2S_DEFAULT_VALUE (0)
|
|
#define AW882XX_OVP2S_DEFAULT \
|
|
(AW882XX_OVP2S_DEFAULT_VALUE<<AW882XX_OVP2S_START_BIT)
|
|
|
|
/* UVLS bit 14 (SYSST 0x01) */
|
|
#define AW882XX_UVLS_START_BIT (14)
|
|
#define AW882XX_UVLS_BITS_LEN (1)
|
|
#define AW882XX_UVLS_MASK \
|
|
(~(((1<<AW882XX_UVLS_BITS_LEN)-1)<<AW882XX_UVLS_START_BIT))
|
|
|
|
#define AW882XX_UVLS_VDD_ABOVE_2P8V (0)
|
|
#define AW882XX_UVLS_VDD_ABOVE_2P8V_VALUE \
|
|
(AW882XX_UVLS_VDD_ABOVE_2P8V << AW882XX_UVLS_START_BIT)
|
|
|
|
#define AW882XX_UVLS_VDD_BELOW_2P8V (1)
|
|
#define AW882XX_UVLS_VDD_BELOW_2P8V_VALUE \
|
|
(AW882XX_UVLS_VDD_BELOW_2P8V << AW882XX_UVLS_START_BIT)
|
|
|
|
#define AW882XX_UVLS_DEFAULT_VALUE (0)
|
|
#define AW882XX_UVLS_DEFAULT \
|
|
(AW882XX_UVLS_DEFAULT_VALUE<<AW882XX_UVLS_START_BIT)
|
|
|
|
/* ADPS bit 13 (SYSST 0x01) */
|
|
#define AW882XX_ADPS_START_BIT (13)
|
|
#define AW882XX_ADPS_BITS_LEN (1)
|
|
#define AW882XX_ADPS_MASK \
|
|
(~(((1<<AW882XX_ADPS_BITS_LEN)-1)<<AW882XX_ADPS_START_BIT))
|
|
|
|
#define AW882XX_ADPS_TRANSPARENT (0)
|
|
#define AW882XX_ADPS_TRANSPARENT_VALUE \
|
|
(AW882XX_ADPS_TRANSPARENT << AW882XX_ADPS_START_BIT)
|
|
#define AW882XX_ADPS_BOOST (1)
|
|
#define AW882XX_ADPS_BOOST_VALUE \
|
|
(AW882XX_ADPS_BOOST << AW882XX_ADPS_START_BIT)
|
|
|
|
#define AW882XX_ADPS_DEFAULT_VALUE (0)
|
|
#define AW882XX_ADPS_DEFAULT \
|
|
(AW882XX_ADPS_DEFAULT_VALUE<<AW882XX_ADPS_START_BIT)
|
|
|
|
/* BSTOCS bit 11 (SYSST 0x01) */
|
|
#define AW882XX_BSTOCS_START_BIT (11)
|
|
#define AW882XX_BSTOCS_BITS_LEN (1)
|
|
#define AW882XX_BSTOCS_MASK \
|
|
(~(((1<<AW882XX_BSTOCS_BITS_LEN)-1)<<AW882XX_BSTOCS_START_BIT))
|
|
|
|
#define AW882XX_BSTOCS_NONE (0)
|
|
#define AW882XX_BSTOCS_NONE_VALUE \
|
|
(AW882XX_BSTOCS_NONE << AW882XX_BSTOCS_START_BIT)
|
|
#define AW882XX_BSTOCS_TRIG (1)
|
|
#define AW882XX_BSTOCS_TRIG_VALUE \
|
|
(AW882XX_BSTOCS_TRIG << AW882XX_BSTOCS_START_BIT)
|
|
|
|
#define AW882XX_BSTOCS_DEFAULT_VALUE (0)
|
|
#define AW882XX_BSTOCS_DEFAULT \
|
|
(AW882XX_BSTOCS_DEFAULT_VALUE<<AW882XX_BSTOCS_START_BIT)
|
|
|
|
/* OVPS bit 10 (SYSST 0x01) */
|
|
#define AW882XX_OVPS_START_BIT (10)
|
|
#define AW882XX_OVPS_BITS_LEN (1)
|
|
#define AW882XX_OVPS_MASK \
|
|
(~(((1<<AW882XX_OVPS_BITS_LEN)-1)<<AW882XX_OVPS_START_BIT))
|
|
|
|
#define AW882XX_OVPS_NONE (0)
|
|
#define AW882XX_OVPS_NONE_VALUE \
|
|
(AW882XX_OVPS_NONE << AW882XX_OVPS_START_BIT)
|
|
#define AW882XX_OVPS_TRIG (1)
|
|
#define AW882XX_OVPS_NONE_VALUE \
|
|
(AW882XX_OVPS_NONE << AW882XX_OVPS_START_BIT)
|
|
|
|
#define AW882XX_OVPS_DEFAULT_VALUE (0)
|
|
#define AW882XX_OVPS_DEFAULT \
|
|
(AW882XX_OVPS_DEFAULT_VALUE<<AW882XX_OVPS_START_BIT)
|
|
|
|
/* BSTS bit 9 (SYSST 0x01) */
|
|
#define AW882XX_BSTS_START_BIT (9)
|
|
#define AW882XX_BSTS_BITS_LEN (1)
|
|
#define AW882XX_BSTS_MASK \
|
|
(~(((1<<AW882XX_BSTS_BITS_LEN)-1)<<AW882XX_BSTS_START_BIT))
|
|
|
|
#define AW882XX_BSTS_NOT_FINISHED (0)
|
|
#define AW882XX_BSTS_NOT_FINISHED_VALUE \
|
|
(AW882XX_BSTS_NOT_FINISHED << AW882XX_BSTS_START_BIT)
|
|
#define AW882XX_BSTS_FINISHED (1)
|
|
#define AW882XX_BSTS_FINISHED_VALUE \
|
|
(AW882XX_BSTS_FINISHED << AW882XX_BSTS_START_BIT)
|
|
|
|
#define AW882XX_BSTS_DEFAULT_VALUE (0)
|
|
#define AW882XX_BSTS_DEFAULT \
|
|
(AW882XX_BSTS_DEFAULT_VALUE<<AW882XX_BSTS_START_BIT)
|
|
|
|
/* SWS bit 8 (SYSST 0x01) */
|
|
#define AW882XX_SWS_START_BIT (8)
|
|
#define AW882XX_SWS_BITS_LEN (1)
|
|
#define AW882XX_SWS_MASK \
|
|
(~(((1<<AW882XX_SWS_BITS_LEN)-1)<<AW882XX_SWS_START_BIT))
|
|
|
|
#define AW882XX_SWS_NOT_SWITCHING (0)
|
|
#define AW882XX_SWS_NOT_SWITCHING_VALUE \
|
|
(AW882XX_SWS_NOT_SWITCHING << AW882XX_SWS_START_BIT)
|
|
#define AW882XX_SWS_SWITCHING (1)
|
|
#define AW882XX_SWS_SWITCHING_VALUE \
|
|
(AW882XX_SWS_SWITCHING << AW882XX_SWS_START_BIT)
|
|
|
|
#define AW882XX_SWS_DEFAULT_VALUE (0)
|
|
#define AW882XX_SWS_DEFAULT \
|
|
(AW882XX_SWS_DEFAULT_VALUE<<AW882XX_SWS_START_BIT)
|
|
|
|
/* CLIPS bit 7 (SYSST 0x01) */
|
|
#define AW882XX_CLIPS_START_BIT (7)
|
|
#define AW882XX_CLIPS_BITS_LEN (1)
|
|
#define AW882XX_CLIPS_MASK \
|
|
(~(((1<<AW882XX_CLIPS_BITS_LEN)-1)<<AW882XX_CLIPS_START_BIT))
|
|
|
|
#define AW882XX_CLIPS_NOT_CLIPPING (0)
|
|
#define AW882XX_CLIPS_NOT_CLIPPING_VALUE \
|
|
(AW882XX_CLIPS_NOT_CLIPPING << AW882XX_CLIPS_START_BIT)
|
|
#define AW882XX_CLIPS_CLIPPING (1)
|
|
#define AW882XX_CLIPS_CLIPPING_VALUE \
|
|
(AW882XX_CLIPS_CLIPPING << AW882XX_CLIPS_START_BIT)
|
|
|
|
#define AW882XX_CLIPS_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLIPS_DEFAULT \
|
|
(AW882XX_CLIPS_DEFAULT_VALUE<<AW882XX_CLIPS_START_BIT)
|
|
|
|
/* NOCLKS bit 5 (SYSST 0x01) */
|
|
#define AW882XX_NOCLKS_START_BIT (5)
|
|
#define AW882XX_NOCLKS_BITS_LEN (1)
|
|
#define AW882XX_NOCLKS_MASK \
|
|
(~(((1<<AW882XX_NOCLKS_BITS_LEN)-1)<<AW882XX_NOCLKS_START_BIT))
|
|
|
|
#define AW882XX_NOCLKS_NONE (0)
|
|
#define AW882XX_NOCLKS_NONE_VALUE \
|
|
(AW882XX_NOCLKS_NONE << AW882XX_NOCLKS_START_BIT)
|
|
#define AW882XX_NOCLKS_TRIG (1)
|
|
#define AW882XX_NOCLKS_TRIG_VALUE \
|
|
(AW882XX_NOCLKS_NONE << AW882XX_NOCLKS_START_BIT)
|
|
|
|
#define AW882XX_NOCLKS_DEFAULT_VALUE (0)
|
|
#define AW882XX_NOCLKS_DEFAULT \
|
|
(AW882XX_NOCLKS_DEFAULT_VALUE<<AW882XX_NOCLKS_START_BIT)
|
|
|
|
/* CLKS bit 4 (SYSST 0x01) */
|
|
#define AW882XX_CLKS_START_BIT (4)
|
|
#define AW882XX_CLKS_BITS_LEN (1)
|
|
#define AW882XX_CLKS_MASK \
|
|
(~(((1<<AW882XX_CLKS_BITS_LEN)-1)<<AW882XX_CLKS_START_BIT))
|
|
|
|
#define AW882XX_CLKS_NONE (0)
|
|
#define AW882XX_CLKS_NONE_VALUE \
|
|
(AW882XX_CLKS_NONE << AW882XX_CLKS_START_BIT)
|
|
#define AW882XX_CLKS_TRIG (1)
|
|
#define AW882XX_CLKS_TRIG_VALUE \
|
|
(AW882XX_CLKS_TRIG << AW882XX_CLKS_START_BIT)
|
|
|
|
#define AW882XX_CLKS_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLKS_DEFAULT \
|
|
(AW882XX_CLKS_DEFAULT_VALUE<<AW882XX_CLKS_START_BIT)
|
|
|
|
/* OCDS bit 3 (SYSST 0x01) */
|
|
#define AW882XX_OCDS_START_BIT (3)
|
|
#define AW882XX_OCDS_BITS_LEN (1)
|
|
#define AW882XX_OCDS_MASK \
|
|
(~(((1<<AW882XX_OCDS_BITS_LEN)-1)<<AW882XX_OCDS_START_BIT))
|
|
|
|
#define AW882XX_OCDS_NONE (0)
|
|
#define AW882XX_OCDS_NONE_VALUE \
|
|
(AW882XX_OCDS_NONE << AW882XX_OCDS_START_BIT)
|
|
#define AW882XX_OCDS_TRIG (1)
|
|
#define AW882XX_OCDS_TRIG_VALUE \
|
|
(AW882XX_OCDS_TRIG << AW882XX_OCDS_START_BIT)
|
|
|
|
#define AW882XX_OCDS_DEFAULT_VALUE (0)
|
|
#define AW882XX_OCDS_DEFAULT \
|
|
(AW882XX_OCDS_DEFAULT_VALUE<<AW882XX_OCDS_START_BIT)
|
|
|
|
/* CLIP_PRES bit 2 (SYSST 0x01) */
|
|
#define AW882XX_CLIP_PRES_START_BIT (2)
|
|
#define AW882XX_CLIP_PRES_BITS_LEN (1)
|
|
#define AW882XX_CLIP_PRES_MASK \
|
|
(~(((1<<AW882XX_CLIP_PRES_BITS_LEN)-1)<<AW882XX_CLIP_PRES_START_BIT))
|
|
|
|
#define AW882XX_CLIP_PRES_NONE (0)
|
|
#define AW882XX_CLIP_PRES_NONE_VALUE \
|
|
(AW882XX_CLIP_PRES_NONE << AW882XX_CLIP_PRES_START_BIT)
|
|
#define AW882XX_CLIP_PRES_TRIG (1)
|
|
#define AW882XX_CLIP_PRES_TRIG_VALUE \
|
|
(AW882XX_CLIP_PRES_TRIG << AW882XX_CLIP_PRES_START_BIT)
|
|
|
|
#define AW882XX_CLIP_PRES_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLIP_PRES_DEFAULT \
|
|
(AW882XX_CLIP_PRES_DEFAULT_VALUE<<AW882XX_CLIP_PRES_START_BIT)
|
|
|
|
/* OTHS bit 1 (SYSST 0x01) */
|
|
#define AW882XX_OTHS_START_BIT (1)
|
|
#define AW882XX_OTHS_BITS_LEN (1)
|
|
#define AW882XX_OTHS_MASK \
|
|
(~(((1<<AW882XX_OTHS_BITS_LEN)-1)<<AW882XX_OTHS_START_BIT))
|
|
|
|
#define AW882XX_OTHS_NONE (0)
|
|
#define AW882XX_OTHS_NONE_VALUE \
|
|
(AW882XX_OTHS_NONE << AW882XX_OTHS_START_BIT)
|
|
#define AW882XX_OTHS_TRIG (1)
|
|
#define AW882XX_OTHS_TRIG_VALUE \
|
|
(AW882XX_OTHS_TRIG << AW882XX_OTHS_START_BIT)
|
|
|
|
#define AW882XX_OTHS_DEFAULT_VALUE (0)
|
|
#define AW882XX_OTHS_DEFAULT \
|
|
(AW882XX_OTHS_DEFAULT_VALUE<<AW882XX_OTHS_START_BIT)
|
|
|
|
/* PLLS bit 0 (SYSST 0x01) */
|
|
#define AW882XX_PLLS_START_BIT (0)
|
|
#define AW882XX_PLLS_BITS_LEN (1)
|
|
#define AW882XX_PLLS_MASK \
|
|
(~(((1<<AW882XX_PLLS_BITS_LEN)-1)<<AW882XX_PLLS_START_BIT))
|
|
|
|
#define AW882XX_PLLS_UNLOCKED (0)
|
|
#define AW882XX_PLLS_UNLOCKED_VALUE \
|
|
(AW882XX_PLLS_UNLOCKED << AW882XX_PLLS_START_BIT)
|
|
#define AW882XX_PLLS_LOCKED (1)
|
|
#define AW882XX_PLLS_LOCKED_VALUE \
|
|
(AW882XX_PLLS_LOCKED << AW882XX_PLLS_START_BIT)
|
|
|
|
#define AW882XX_PLLS_DEFAULT_VALUE (0)
|
|
#define AW882XX_PLLS_DEFAULT \
|
|
(AW882XX_PLLS_DEFAULT_VALUE<<AW882XX_PLLS_START_BIT)
|
|
|
|
#define AW882XX_SYSST_CHECK_MASK \
|
|
(~(AW882XX_UVLS_VDD_BELOW_2P8V_VALUE | \
|
|
AW882XX_BSTOCS_TRIG_VALUE | \
|
|
AW882XX_BSTS_FINISHED_VALUE | \
|
|
AW882XX_SWS_SWITCHING_VALUE | \
|
|
AW882XX_NOCLKS_TRIG_VALUE | \
|
|
AW882XX_CLKS_TRIG_VALUE | \
|
|
AW882XX_OCDS_TRIG_VALUE | \
|
|
AW882XX_OTHS_TRIG_VALUE | \
|
|
AW882XX_PLLS_LOCKED_VALUE))
|
|
|
|
#define AW882XX_SYSST_CHECK \
|
|
(AW882XX_CLKS_TRIG_VALUE | \
|
|
AW882XX_PLLS_LOCKED_VALUE)
|
|
|
|
#define AW882XX_IIS_CHECK_MASK \
|
|
(~(AW882XX_UVLS_VDD_BELOW_2P8V_VALUE | \
|
|
AW882XX_NOCLKS_TRIG_VALUE | \
|
|
AW882XX_CLKS_TRIG_VALUE | \
|
|
AW882XX_OCDS_TRIG_VALUE | \
|
|
AW882XX_OTHS_TRIG_VALUE | \
|
|
AW882XX_PLLS_LOCKED_VALUE))
|
|
|
|
#define AW882XX_IIS_CHECK \
|
|
(AW882XX_CLKS_TRIG_VALUE | \
|
|
AW882XX_PLLS_LOCKED_VALUE)
|
|
|
|
/* default value of SYSST (0x01) */
|
|
/* #define AW882XX_SYSST_DEFAULT (0x0000) */
|
|
|
|
/* SYSINT (0x02) detail */
|
|
/* OVP2I bit 15 (SYSINT 0x02) */
|
|
#define AW882XX_OVP2I_START_BIT (15)
|
|
#define AW882XX_OVP2I_BITS_LEN (1)
|
|
#define AW882XX_OVP2I_MASK \
|
|
(~(((1<<AW882XX_OVP2I_BITS_LEN)-1)<<AW882XX_OVP2I_START_BIT))
|
|
|
|
#define AW882XX_OVP2I_DEFAULT_VALUE (0)
|
|
#define AW882XX_OVP2I_DEFAULT \
|
|
(AW882XX_OVP2I_DEFAULT_VALUE<<AW882XX_OVP2I_START_BIT)
|
|
|
|
/* UVLI bit 14 (SYSINT 0x02) */
|
|
#define AW882XX_UVLI_START_BIT (14)
|
|
#define AW882XX_UVLI_BITS_LEN (1)
|
|
#define AW882XX_UVLI_MASK \
|
|
(~(((1<<AW882XX_UVLI_BITS_LEN)-1)<<AW882XX_UVLI_START_BIT))
|
|
|
|
#define AW882XX_UVLI_DEFAULT_VALUE (0)
|
|
#define AW882XX_UVLI_DEFAULT \
|
|
(AW882XX_UVLI_DEFAULT_VALUE<<AW882XX_UVLI_START_BIT)
|
|
|
|
/* ADPI bit 13 (SYSINT 0x02) */
|
|
#define AW882XX_ADPI_START_BIT (13)
|
|
#define AW882XX_ADPI_BITS_LEN (1)
|
|
#define AW882XX_ADPI_MASK \
|
|
(~(((1<<AW882XX_ADPI_BITS_LEN)-1)<<AW882XX_ADPI_START_BIT))
|
|
|
|
#define AW882XX_ADPI_DEFAULT_VALUE (0)
|
|
#define AW882XX_ADPI_DEFAULT \
|
|
(AW882XX_ADPI_DEFAULT_VALUE<<AW882XX_ADPI_START_BIT)
|
|
|
|
/* BSTOCI bit 11 (SYSINT 0x02) */
|
|
#define AW882XX_BSTOCI_START_BIT (11)
|
|
#define AW882XX_BSTOCI_BITS_LEN (1)
|
|
#define AW882XX_BSTOCI_MASK \
|
|
(~(((1<<AW882XX_BSTOCI_BITS_LEN)-1)<<AW882XX_BSTOCI_START_BIT))
|
|
|
|
#define AW882XX_BSTOCI_DEFAULT_VALUE (0)
|
|
#define AW882XX_BSTOCI_DEFAULT \
|
|
(AW882XX_BSTOCI_DEFAULT_VALUE<<AW882XX_BSTOCI_START_BIT)
|
|
|
|
/* OVPI bit 10 (SYSINT 0x02) */
|
|
#define AW882XX_OVPI_START_BIT (10)
|
|
#define AW882XX_OVPI_BITS_LEN (1)
|
|
#define AW882XX_OVPI_MASK \
|
|
(~(((1<<AW882XX_OVPI_BITS_LEN)-1)<<AW882XX_OVPI_START_BIT))
|
|
|
|
#define AW882XX_OVPI_DEFAULT_VALUE (0)
|
|
#define AW882XX_OVPI_DEFAULT \
|
|
(AW882XX_OVPI_DEFAULT_VALUE<<AW882XX_OVPI_START_BIT)
|
|
|
|
/* BSTI bit 9 (SYSINT 0x02) */
|
|
#define AW882XX_BSTI_START_BIT (9)
|
|
#define AW882XX_BSTI_BITS_LEN (1)
|
|
#define AW882XX_BSTI_MASK \
|
|
(~(((1<<AW882XX_BSTI_BITS_LEN)-1)<<AW882XX_BSTI_START_BIT))
|
|
|
|
#define AW882XX_BSTI_DEFAULT_VALUE (0)
|
|
#define AW882XX_BSTI_DEFAULT \
|
|
(AW882XX_BSTI_DEFAULT_VALUE<<AW882XX_BSTI_START_BIT)
|
|
|
|
/* SWI bit 8 (SYSINT 0x02) */
|
|
#define AW882XX_SWI_START_BIT (8)
|
|
#define AW882XX_SWI_BITS_LEN (1)
|
|
#define AW882XX_SWI_MASK \
|
|
(~(((1<<AW882XX_SWI_BITS_LEN)-1)<<AW882XX_SWI_START_BIT))
|
|
|
|
#define AW882XX_SWI_DEFAULT_VALUE (0)
|
|
#define AW882XX_SWI_DEFAULT \
|
|
(AW882XX_SWI_DEFAULT_VALUE<<AW882XX_SWI_START_BIT)
|
|
|
|
/* CLIPI bit 7 (SYSINT 0x02) */
|
|
#define AW882XX_CLIPI_START_BIT (7)
|
|
#define AW882XX_CLIPI_BITS_LEN (1)
|
|
#define AW882XX_CLIPI_MASK \
|
|
(~(((1<<AW882XX_CLIPI_BITS_LEN)-1)<<AW882XX_CLIPI_START_BIT))
|
|
|
|
#define AW882XX_CLIPI_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLIPI_DEFAULT \
|
|
(AW882XX_CLIPI_DEFAULT_VALUE<<AW882XX_CLIPI_START_BIT)
|
|
|
|
/* NOCLKI bit 5 (SYSINT 0x02) */
|
|
#define AW882XX_NOCLKI_START_BIT (5)
|
|
#define AW882XX_NOCLKI_BITS_LEN (1)
|
|
#define AW882XX_NOCLKI_MASK \
|
|
(~(((1<<AW882XX_NOCLKI_BITS_LEN)-1)<<AW882XX_NOCLKI_START_BIT))
|
|
|
|
#define AW882XX_NOCLKI_DEFAULT_VALUE (0)
|
|
#define AW882XX_NOCLKI_DEFAULT \
|
|
(AW882XX_NOCLKI_DEFAULT_VALUE<<AW882XX_NOCLKI_START_BIT)
|
|
|
|
/* CLKI bit 4 (SYSINT 0x02) */
|
|
#define AW882XX_CLKI_START_BIT (4)
|
|
#define AW882XX_CLKI_BITS_LEN (1)
|
|
#define AW882XX_CLKI_MASK \
|
|
(~(((1<<AW882XX_CLKI_BITS_LEN)-1)<<AW882XX_CLKI_START_BIT))
|
|
|
|
#define AW882XX_CLKI_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLKI_DEFAULT \
|
|
(AW882XX_CLKI_DEFAULT_VALUE<<AW882XX_CLKI_START_BIT)
|
|
|
|
/* OCDI bit 3 (SYSINT 0x02) */
|
|
#define AW882XX_OCDI_START_BIT (3)
|
|
#define AW882XX_OCDI_BITS_LEN (1)
|
|
#define AW882XX_OCDI_MASK \
|
|
(~(((1<<AW882XX_OCDI_BITS_LEN)-1)<<AW882XX_OCDI_START_BIT))
|
|
|
|
#define AW882XX_OCDI_DEFAULT_VALUE (0)
|
|
#define AW882XX_OCDI_DEFAULT \
|
|
(AW882XX_OCDI_DEFAULT_VALUE<<AW882XX_OCDI_START_BIT)
|
|
|
|
/* CLIP_PREI bit 2 (SYSINT 0x02) */
|
|
#define AW882XX_CLIP_PREI_START_BIT (2)
|
|
#define AW882XX_CLIP_PREI_BITS_LEN (1)
|
|
#define AW882XX_CLIP_PREI_MASK \
|
|
(~(((1<<AW882XX_CLIP_PREI_BITS_LEN)-1)<<AW882XX_CLIP_PREI_START_BIT))
|
|
|
|
#define AW882XX_CLIP_PREI_DEFAULT_VALUE (0)
|
|
#define AW882XX_CLIP_PREI_DEFAULT \
|
|
(AW882XX_CLIP_PREI_DEFAULT_VALUE<<AW882XX_CLIP_PREI_START_BIT)
|
|
|
|
/* OTHI bit 1 (SYSINT 0x02) */
|
|
#define AW882XX_OTHI_START_BIT (1)
|
|
#define AW882XX_OTHI_BITS_LEN (1)
|
|
#define AW882XX_OTHI_MASK \
|
|
(~(((1<<AW882XX_OTHI_BITS_LEN)-1)<<AW882XX_OTHI_START_BIT))
|
|
|
|
#define AW882XX_OTHI_DEFAULT_VALUE (0)
|
|
#define AW882XX_OTHI_DEFAULT \
|
|
(AW882XX_OTHI_DEFAULT_VALUE<<AW882XX_OTHI_START_BIT)
|
|
|
|
/* PLLI bit 0 (SYSINT 0x02) */
|
|
#define AW882XX_PLLI_START_BIT (0)
|
|
#define AW882XX_PLLI_BITS_LEN (1)
|
|
#define AW882XX_PLLI_MASK \
|
|
(~(((1<<AW882XX_PLLI_BITS_LEN)-1)<<AW882XX_PLLI_START_BIT))
|
|
|
|
#define AW882XX_PLLI_DEFAULT_VALUE (0)
|
|
#define AW882XX_PLLI_DEFAULT \
|
|
(AW882XX_PLLI_DEFAULT_VALUE<<AW882XX_PLLI_START_BIT)
|
|
|
|
/* default value of SYSINT (0x02) */
|
|
/* #define AW882XX_SYSINT_DEFAULT (0x0000) */
|
|
|
|
/* SYSINTM (0x03) detail */
|
|
/* OVP2M bit 15 (SYSINTM 0x03) */
|
|
#define AW882XX_OVP2M_START_BIT (15)
|
|
#define AW882XX_OVP2M_BITS_LEN (1)
|
|
#define AW882XX_OVP2M_MASK \
|
|
(~(((1<<AW882XX_OVP2M_BITS_LEN)-1)<<AW882XX_OVP2M_START_BIT))
|
|
|
|
#define AW882XX_OVP2M_DEFAULT_VALUE (1)
|
|
#define AW882XX_OVP2M_DEFAULT \
|
|
(AW882XX_OVP2M_DEFAULT_VALUE<<AW882XX_OVP2M_START_BIT)
|
|
|
|
/* UVLM bit 14 (SYSINTM 0x03) */
|
|
#define AW882XX_UVLM_START_BIT (14)
|
|
#define AW882XX_UVLM_BITS_LEN (1)
|
|
#define AW882XX_UVLM_MASK \
|
|
(~(((1<<AW882XX_UVLM_BITS_LEN)-1)<<AW882XX_UVLM_START_BIT))
|
|
|
|
#define AW882XX_UVLM_DEFAULT_VALUE (1)
|
|
#define AW882XX_UVLM_DEFAULT \
|
|
(AW882XX_UVLM_DEFAULT_VALUE<<AW882XX_UVLM_START_BIT)
|
|
|
|
/* ADPM bit 13 (SYSINTM 0x03) */
|
|
#define AW882XX_ADPM_START_BIT (13)
|
|
#define AW882XX_ADPM_BITS_LEN (1)
|
|
#define AW882XX_ADPM_MASK \
|
|
(~(((1<<AW882XX_ADPM_BITS_LEN)-1)<<AW882XX_ADPM_START_BIT))
|
|
|
|
#define AW882XX_ADPM_DEFAULT_VALUE (1)
|
|
#define AW882XX_ADPM_DEFAULT \
|
|
(AW882XX_ADPM_DEFAULT_VALUE<<AW882XX_ADPM_START_BIT)
|
|
|
|
/* BSTOCM bit 11 (SYSINTM 0x03) */
|
|
#define AW882XX_BSTOCM_START_BIT (11)
|
|
#define AW882XX_BSTOCM_BITS_LEN (1)
|
|
#define AW882XX_BSTOCM_MASK \
|
|
(~(((1<<AW882XX_BSTOCM_BITS_LEN)-1)<<AW882XX_BSTOCM_START_BIT))
|
|
|
|
#define AW882XX_BSTOCM_DEFAULT_VALUE (1)
|
|
#define AW882XX_BSTOCM_DEFAULT \
|
|
(AW882XX_BSTOCM_DEFAULT_VALUE<<AW882XX_BSTOCM_START_BIT)
|
|
|
|
/* OVPM bit 10 (SYSINTM 0x03) */
|
|
#define AW882XX_OVPM_START_BIT (10)
|
|
#define AW882XX_OVPM_BITS_LEN (1)
|
|
#define AW882XX_OVPM_MASK \
|
|
(~(((1<<AW882XX_OVPM_BITS_LEN)-1)<<AW882XX_OVPM_START_BIT))
|
|
|
|
#define AW882XX_OVPM_DEFAULT_VALUE (1)
|
|
#define AW882XX_OVPM_DEFAULT \
|
|
(AW882XX_OVPM_DEFAULT_VALUE<<AW882XX_OVPM_START_BIT)
|
|
|
|
/* BSTM bit 9 (SYSINTM 0x03) */
|
|
#define AW882XX_BSTM_START_BIT (9)
|
|
#define AW882XX_BSTM_BITS_LEN (1)
|
|
#define AW882XX_BSTM_MASK \
|
|
(~(((1<<AW882XX_BSTM_BITS_LEN)-1)<<AW882XX_BSTM_START_BIT))
|
|
|
|
#define AW882XX_BSTM_DEFAULT_VALUE (1)
|
|
#define AW882XX_BSTM_DEFAULT \
|
|
(AW882XX_BSTM_DEFAULT_VALUE<<AW882XX_BSTM_START_BIT)
|
|
|
|
/* SWM bit 8 (SYSINTM 0x03) */
|
|
#define AW882XX_SWM_START_BIT (8)
|
|
#define AW882XX_SWM_BITS_LEN (1)
|
|
#define AW882XX_SWM_MASK \
|
|
(~(((1<<AW882XX_SWM_BITS_LEN)-1)<<AW882XX_SWM_START_BIT))
|
|
|
|
#define AW882XX_SWM_DEFAULT_VALUE (1)
|
|
#define AW882XX_SWM_DEFAULT \
|
|
(AW882XX_SWM_DEFAULT_VALUE<<AW882XX_SWM_START_BIT)
|
|
|
|
/* CLIPM bit 7 (SYSINTM 0x03) */
|
|
#define AW882XX_CLIPM_START_BIT (7)
|
|
#define AW882XX_CLIPM_BITS_LEN (1)
|
|
#define AW882XX_CLIPM_MASK \
|
|
(~(((1<<AW882XX_CLIPM_BITS_LEN)-1)<<AW882XX_CLIPM_START_BIT))
|
|
|
|
#define AW882XX_CLIPM_DEFAULT_VALUE (1)
|
|
#define AW882XX_CLIPM_DEFAULT \
|
|
(AW882XX_CLIPM_DEFAULT_VALUE<<AW882XX_CLIPM_START_BIT)
|
|
|
|
/* NOCLKM bit 5 (SYSINTM 0x03) */
|
|
#define AW882XX_NOCLKM_START_BIT (5)
|
|
#define AW882XX_NOCLKM_BITS_LEN (1)
|
|
#define AW882XX_NOCLKM_MASK \
|
|
(~(((1<<AW882XX_NOCLKM_BITS_LEN)-1)<<AW882XX_NOCLKM_START_BIT))
|
|
|
|
#define AW882XX_NOCLKM_DEFAULT_VALUE (1)
|
|
#define AW882XX_NOCLKM_DEFAULT \
|
|
(AW882XX_NOCLKM_DEFAULT_VALUE<<AW882XX_NOCLKM_START_BIT)
|
|
|
|
/* CLKM bit 4 (SYSINTM 0x03) */
|
|
#define AW882XX_CLKM_START_BIT (4)
|
|
#define AW882XX_CLKM_BITS_LEN (1)
|
|
#define AW882XX_CLKM_MASK \
|
|
(~(((1<<AW882XX_CLKM_BITS_LEN)-1)<<AW882XX_CLKM_START_BIT))
|
|
|
|
#define AW882XX_CLKM_DEFAULT_VALUE (1)
|
|
#define AW882XX_CLKM_DEFAULT \
|
|
(AW882XX_CLKM_DEFAULT_VALUE<<AW882XX_CLKM_START_BIT)
|
|
|
|
/* OCDM bit 3 (SYSINTM 0x03) */
|
|
#define AW882XX_OCDM_START_BIT (3)
|
|
#define AW882XX_OCDM_BITS_LEN (1)
|
|
#define AW882XX_OCDM_MASK \
|
|
(~(((1<<AW882XX_OCDM_BITS_LEN)-1)<<AW882XX_OCDM_START_BIT))
|
|
|
|
#define AW882XX_OCDM_DEFAULT_VALUE (1)
|
|
#define AW882XX_OCDM_DEFAULT \
|
|
(AW882XX_OCDM_DEFAULT_VALUE<<AW882XX_OCDM_START_BIT)
|
|
|
|
/* CLIP_PREM bit 2 (SYSINTM 0x03) */
|
|
#define AW882XX_CLIP_PREM_START_BIT (2)
|
|
#define AW882XX_CLIP_PREM_BITS_LEN (1)
|
|
#define AW882XX_CLIP_PREM_MASK \
|
|
(~(((1<<AW882XX_CLIP_PREM_BITS_LEN)-1)<<AW882XX_CLIP_PREM_START_BIT))
|
|
|
|
#define AW882XX_CLIP_PREM_DEFAULT_VALUE (1)
|
|
#define AW882XX_CLIP_PREM_DEFAULT \
|
|
(AW882XX_CLIP_PREM_DEFAULT_VALUE<<AW882XX_CLIP_PREM_START_BIT)
|
|
|
|
/* OTHM bit 1 (SYSINTM 0x03) */
|
|
#define AW882XX_OTHM_START_BIT (1)
|
|
#define AW882XX_OTHM_BITS_LEN (1)
|
|
#define AW882XX_OTHM_MASK \
|
|
(~(((1<<AW882XX_OTHM_BITS_LEN)-1)<<AW882XX_OTHM_START_BIT))
|
|
|
|
#define AW882XX_OTHM_DEFAULT_VALUE (1)
|
|
#define AW882XX_OTHM_DEFAULT \
|
|
(AW882XX_OTHM_DEFAULT_VALUE<<AW882XX_OTHM_START_BIT)
|
|
|
|
/* PLLM bit 0 (SYSINTM 0x03) */
|
|
#define AW882XX_PLLM_START_BIT (0)
|
|
#define AW882XX_PLLM_BITS_LEN (1)
|
|
#define AW882XX_PLLM_MASK \
|
|
(~(((1<<AW882XX_PLLM_BITS_LEN)-1)<<AW882XX_PLLM_START_BIT))
|
|
|
|
#define AW882XX_PLLM_DEFAULT_VALUE (1)
|
|
#define AW882XX_PLLM_DEFAULT \
|
|
(AW882XX_PLLM_DEFAULT_VALUE<<AW882XX_PLLM_START_BIT)
|
|
|
|
/* default value of SYSINTM (0x03) */
|
|
/* #define AW882XX_SYSINTM_DEFAULT (0xEFBF) */
|
|
|
|
/* SYSCTRL (0x04) detail */
|
|
/* SPK_GAIN bit 14:12 (SYSCTRL 0x04) */
|
|
#define AW882XX_SPK_GAIN_START_BIT (12)
|
|
#define AW882XX_SPK_GAIN_BITS_LEN (3)
|
|
#define AW882XX_SPK_GAIN_MASK \
|
|
(~(((1<<AW882XX_SPK_GAIN_BITS_LEN)-1)<<AW882XX_SPK_GAIN_START_BIT))
|
|
|
|
#define AW882XX_SPK_GAIN_AV7 (0)
|
|
#define AW882XX_SPK_GAIN_AV7_VALUE \
|
|
(AW882XX_SPK_GAIN_AV7 << AW882XX_SPK_GAIN_START_BIT)
|
|
#define AW882XX_SPK_GAIN_AV8 (1)
|
|
#define AW882XX_SPK_GAIN_AV8_VALUE \
|
|
(AW882XX_SPK_GAIN_AV8 << AW882XX_SPK_GAIN_START_BIT)
|
|
#define AW882XX_SPK_GAIN_AV10 (2)
|
|
#define AW882XX_SPK_GAIN_AV10_VALUE \
|
|
(AW882XX_SPK_GAIN_AV10 << AW882XX_SPK_GAIN_START_BIT)
|
|
#define AW882XX_SPK_GAIN_AV14 (3)
|
|
#define AW882XX_SPK_GAIN_AV14_VALUE \
|
|
(AW882XX_SPK_GAIN_AV14 << AW882XX_SPK_GAIN_START_BIT)
|
|
#define AW882XX_SPK_GAIN_AV16 (4)
|
|
#define AW882XX_SPK_GAIN_AV16_VALUE \
|
|
(AW882XX_SPK_GAIN_AV16 << AW882XX_SPK_GAIN_START_BIT)
|
|
#define AW882XX_SPK_GAIN_AV20 (5)
|
|
#define AW882XX_SPK_GAIN_AV20_VALUE \
|
|
(AW882XX_SPK_GAIN_AV20 << AW882XX_SPK_GAIN_START_BIT)
|
|
|
|
#define AW882XX_SPK_GAIN_DEFAULT_VALUE (0x4)
|
|
#define AW882XX_SPK_GAIN_DEFAULT \
|
|
(AW882XX_SPK_GAIN_DEFAULT_VALUE<<AW882XX_SPK_GAIN_START_BIT)
|
|
|
|
/* RCV_GAIN bit 11:10 (SYSCTRL 0x04) */
|
|
#define AW882XX_RCV_GAIN_START_BIT (10)
|
|
#define AW882XX_RCV_GAIN_BITS_LEN (2)
|
|
#define AW882XX_RCV_GAIN_MASK \
|
|
(~(((1<<AW882XX_RCV_GAIN_BITS_LEN)-1)<<AW882XX_RCV_GAIN_START_BIT))
|
|
|
|
#define AW882XX_RCV_GAIN_AV4P5 (0)
|
|
#define AW882XX_RCV_GAIN_AV4P5_VALUE \
|
|
(AW882XX_RCV_GAIN_AV4P5 << AW882XX_RCV_GAIN_START_BIT)
|
|
#define AW882XX_RCV_GAIN_AV5 (1)
|
|
#define AW882XX_RCV_GAIN_AV5_VALUE \
|
|
(AW882XX_RCV_GAIN_AV5 << AW882XX_RCV_GAIN_START_BIT)
|
|
#define AW882XX_RCV_GAIN_AV5P5 (2)
|
|
#define AW882XX_RCV_GAIN_AV5P5_VALUE \
|
|
(AW882XX_RCV_GAIN_AV5P5 << AW882XX_RCV_GAIN_START_BIT)
|
|
#define AW882XX_RCV_GAIN_AV7P5 (3)
|
|
#define AW882XX_RCV_GAIN_AV7P5_VALUE \
|
|
(AW882XX_RCV_GAIN_AV7P5 << AW882XX_RCV_GAIN_START_BIT)
|
|
|
|
#define AW882XX_RCV_GAIN_DEFAULT_VALUE (0)
|
|
#define AW882XX_RCV_GAIN_DEFAULT \
|
|
(AW882XX_RCV_GAIN_DEFAULT_VALUE<<AW882XX_RCV_GAIN_START_BIT)
|
|
|
|
/* INTMODE bit 9 (SYSCTRL 0x04) */
|
|
#define AW882XX_INTMODE_START_BIT (9)
|
|
#define AW882XX_INTMODE_BITS_LEN (1)
|
|
#define AW882XX_INTMODE_MASK \
|
|
(~(((1<<AW882XX_INTMODE_BITS_LEN)-1)<<AW882XX_INTMODE_START_BIT))
|
|
|
|
#define AW882XX_INTMODE_OPENDRAIN (0)
|
|
#define AW882XX_INTMODE_OPENDRAIN_VALUE \
|
|
(AW882XX_INTMODE_OPENDRAIN << AW882XX_INTMODE_START_BIT)
|
|
#define AW882XX_INTMODE_PUSHPULL (1)
|
|
#define AW882XX_INTMODE_PUSHPULL_VALUE \
|
|
(AW882XX_INTMODE_PUSHPULL << AW882XX_INTMODE_START_BIT)
|
|
|
|
#define AW882XX_INTMODE_DEFAULT_VALUE (0)
|
|
#define AW882XX_INTMODE_DEFAULT \
|
|
(AW882XX_INTMODE_DEFAULT_VALUE<<AW882XX_INTMODE_START_BIT)
|
|
|
|
/* INTN bit 8 (SYSCTRL 0x04) */
|
|
#define AW882XX_INTN_START_BIT (8)
|
|
#define AW882XX_INTN_BITS_LEN (1)
|
|
#define AW882XX_INTN_MASK \
|
|
(~(((1<<AW882XX_INTN_BITS_LEN)-1)<<AW882XX_INTN_START_BIT))
|
|
|
|
#define AW882XX_INTN_SYSINT (0)
|
|
#define AW882XX_INTN_SYSINT_VALUE \
|
|
(AW882XX_INTN_SYSINT << AW882XX_INTN_START_BIT)
|
|
#define AW882XX_INTN_SYSST (1)
|
|
#define AW882XX_INTN_SYSST_VALUE \
|
|
(AW882XX_INTN_SYSST << AW882XX_INTN_START_BIT)
|
|
|
|
#define AW882XX_INTN_DEFAULT_VALUE (0)
|
|
#define AW882XX_INTN_DEFAULT \
|
|
(AW882XX_INTN_DEFAULT_VALUE<<AW882XX_INTN_START_BIT)
|
|
|
|
/* RCV_MODE bit 7 (SYSCTRL 0x04) */
|
|
#define AW882XX_RCV_MODE_START_BIT (7)
|
|
#define AW882XX_RCV_MODE_BITS_LEN (1)
|
|
#define AW882XX_RCV_MODE_MASK \
|
|
(~(((1<<AW882XX_RCV_MODE_BITS_LEN)-1)<<AW882XX_RCV_MODE_START_BIT))
|
|
|
|
#define AW882XX_RCV_MODE_SPEAKER (0)
|
|
#define AW882XX_RCV_MODE_SPEAKER_MODE \
|
|
(AW882XX_RCV_MODE_SPEAKER_MODE << AW882XX_RCV_MODE_START_BIT)
|
|
#define AW882XX_RCV_MODE_RECEIVER (1)
|
|
#define AW882XX_RCV_MODE_RECEIVER_MODE \
|
|
(AW882XX_RCV_MODE_RECEIVER_MODE << AW882XX_RCV_MODE_START_BIT)
|
|
|
|
#define AW882XX_RCV_MODE_DEFAULT_VALUE (0)
|
|
#define AW882XX_RCV_MODE_DEFAULT \
|
|
(AW882XX_RCV_MODE_DEFAULT_VALUE<<AW882XX_RCV_MODE_START_BIT)
|
|
|
|
/* I2SEN bit 6 (SYSCTRL 0x04) */
|
|
#define AW882XX_I2SEN_START_BIT (6)
|
|
#define AW882XX_I2SEN_BITS_LEN (1)
|
|
#define AW882XX_I2SEN_MASK \
|
|
(~(((1<<AW882XX_I2SEN_BITS_LEN)-1)<<AW882XX_I2SEN_START_BIT))
|
|
|
|
#define AW882XX_I2SEN_DISABLE (0)
|
|
#define AW882XX_I2SEN_DISABLE_VALUE \
|
|
(AW882XX_I2SEN_DISABLE << AW882XX_I2SEN_START_BIT)
|
|
#define AW882XX_I2SEN_ENABLE (1)
|
|
#define AW882XX_I2SEN_ENABLE_VALUE \
|
|
(AW882XX_I2SEN_ENABLE << AW882XX_I2SEN_START_BIT)
|
|
|
|
#define AW882XX_I2SEN_DEFAULT_VALUE (0)
|
|
#define AW882XX_I2SEN_DEFAULT \
|
|
(AW882XX_I2SEN_DEFAULT_VALUE<<AW882XX_I2SEN_START_BIT)
|
|
|
|
/* WSINV bit 5 (SYSCTRL 0x04) */
|
|
#define AW882XX_WSINV_START_BIT (5)
|
|
#define AW882XX_WSINV_BITS_LEN (1)
|
|
#define AW882XX_WSINV_MASK \
|
|
(~(((1<<AW882XX_WSINV_BITS_LEN)-1)<<AW882XX_WSINV_START_BIT))
|
|
|
|
#define AW882XX_WSINV_NO_SWITCH (0)
|
|
#define AW882XX_WSINV_NO_SWITCH_VALUE \
|
|
(AW882XX_WSINV_NO_SWITCH << AW882XX_WSINV_START_BIT)
|
|
#define AW882XX_WSINV_LEFTRIGHT_SWITCH (1)
|
|
#define AW882XX_WSINV_LEFTRIGHT_SWITCH_VALUE \
|
|
(AW882XX_WSINV_LEFTRIGHT_SWITCH << AW882XX_WSINV_START_BIT)
|
|
|
|
#define AW882XX_WSINV_DEFAULT_VALUE (0)
|
|
#define AW882XX_WSINV_DEFAULT \
|
|
(AW882XX_WSINV_DEFAULT_VALUE<<AW882XX_WSINV_START_BIT)
|
|
|
|
/* BCKINV bit 4 (SYSCTRL 0x04) */
|
|
#define AW882XX_BCKINV_START_BIT (4)
|
|
#define AW882XX_BCKINV_BITS_LEN (1)
|
|
#define AW882XX_BCKINV_MASK \
|
|
(~(((1<<AW882XX_BCKINV_BITS_LEN)-1)<<AW882XX_BCKINV_START_BIT))
|
|
|
|
#define AW882XX_BCKINV_NOT_INVERT (0)
|
|
#define AW882XX_BCKINV_NOT_INVERT_VALUE \
|
|
(AW882XX_BCKINV_NOT_INVERT << AW882XX_BCKINV_START_BIT)
|
|
#define AW882XX_BCKINV_INVERTED (1)
|
|
#define AW882XX_BCKINV_INVERTED_VALUE \
|
|
(AW882XX_BCKINV_INVERTED << AW882XX_BCKINV_START_BIT)
|
|
|
|
#define AW882XX_BCKINV_DEFAULT_VALUE (0)
|
|
#define AW882XX_BCKINV_DEFAULT \
|
|
(AW882XX_BCKINV_DEFAULT_VALUE<<AW882XX_BCKINV_START_BIT)
|
|
|
|
/* IPLL bit 3 (SYSCTRL 0x04) */
|
|
#define AW882XX_IPLL_START_BIT (3)
|
|
#define AW882XX_IPLL_BITS_LEN (1)
|
|
#define AW882XX_IPLL_MASK \
|
|
(~(((1<<AW882XX_IPLL_BITS_LEN)-1)<<AW882XX_IPLL_START_BIT))
|
|
|
|
#define AW882XX_IPLL_BCK (0)
|
|
#define AW882XX_IPLL_BCK_VALUE \
|
|
(AW882XX_IPLL_BCK << AW882XX_IPLL_START_BIT)
|
|
#define AW882XX_IPLL_WCK (1)
|
|
#define AW882XX_IPLL_WCK_VALUE \
|
|
(AW882XX_IPLL_WWCK << AW882XX_IPLL_START_BIT)
|
|
|
|
#define AW882XX_IPLL_DEFAULT_VALUE (0)
|
|
#define AW882XX_IPLL_DEFAULT \
|
|
(AW882XX_IPLL_DEFAULT_VALUE<<AW882XX_IPLL_START_BIT)
|
|
|
|
/* AMPPD bit 1 (SYSCTRL 0x04) */
|
|
#define AW882XX_AMPPD_START_BIT (1)
|
|
#define AW882XX_AMPPD_BITS_LEN (1)
|
|
#define AW882XX_AMPPD_MASK \
|
|
(~(((1<<AW882XX_AMPPD_BITS_LEN)-1)<<AW882XX_AMPPD_START_BIT))
|
|
|
|
#define AW882XX_AMPPD_NORMAL_WORKING (0)
|
|
#define AW882XX_AMPPD_NORMAL_WORKING_VALUE \
|
|
(AW882XX_AMPPD_NORMAL_WORKING << AW882XX_AMPPD_START_BIT)
|
|
#define AW882XX_AMPPD_POWER_DOWN (1)
|
|
#define AW882XX_AMPPD_POWER_DOWN_VALUE \
|
|
(AW882XX_AMPPD_POWER_DOWN << AW882XX_AMPPD_START_BIT)
|
|
|
|
#define AW882XX_AMPPD_DEFAULT_VALUE (1)
|
|
#define AW882XX_AMPPD_DEFAULT \
|
|
(AW882XX_AMPPD_DEFAULT_VALUE<<AW882XX_AMPPD_START_BIT)
|
|
|
|
/* PWDN bit 0 (SYSCTRL 0x04) */
|
|
#define AW882XX_PWDN_START_BIT (0)
|
|
#define AW882XX_PWDN_BITS_LEN (1)
|
|
#define AW882XX_PWDN_MASK \
|
|
(~(((1<<AW882XX_PWDN_BITS_LEN)-1)<<AW882XX_PWDN_START_BIT))
|
|
|
|
#define AW882XX_PWDN_NORMAL_WORKING (0)
|
|
#define AW882XX_PWDN_NORMAL_WORKING_VALUE \
|
|
(AW882XX_PWDN_NORMAL_WORKING << AW882XX_PWDN_START_BIT)
|
|
#define AW882XX_PWDN_POWER_DOWN (1)
|
|
#define AW882XX_PWDN_POWER_DOWN_VALUE \
|
|
(AW882XX_PWDN_POWER_DOWN << AW882XX_PWDN_START_BIT)
|
|
|
|
#define AW882XX_PWDN_DEFAULT_VALUE (1)
|
|
#define AW882XX_PWDN_DEFAULT \
|
|
(AW882XX_PWDN_DEFAULT_VALUE<<AW882XX_PWDN_START_BIT)
|
|
|
|
/* default value of SYSCTRL (0x04) */
|
|
/* #define AW882XX_SYSCTRL_DEFAULT (0x4003) */
|
|
|
|
/* SYSCTRL2 (0x05) detail */
|
|
/* RMSE bit 7 (SYSCTRL2 0x05) */
|
|
#define AW882XX_RMSE_START_BIT (7)
|
|
#define AW882XX_RMSE_BITS_LEN (1)
|
|
#define AW882XX_RMSE_MASK \
|
|
(~(((1<<AW882XX_RMSE_BITS_LEN)-1)<<AW882XX_RMSE_START_BIT))
|
|
|
|
#define AW882XX_RMSE_DISABLE (0)
|
|
#define AW882XX_RMSE_DISABLE_VALUE \
|
|
(AW882XX_RMSE_DISABLE << AW882XX_RMSE_START_BIT)
|
|
#define AW882XX_RMSE_ENABLE (1)
|
|
#define AW882XX_RMSE_ENABLE_VALUE \
|
|
(AW882XX_RMSE_ENABLE << AW882XX_RMSE_START_BIT)
|
|
|
|
#define AW882XX_RMSE_DEFAULT_VALUE (0)
|
|
#define AW882XX_RMSE_DEFAULT \
|
|
(AW882XX_RMSE_DEFAULT_VALUE<<AW882XX_RMSE_START_BIT)
|
|
|
|
/* HAGCE bit 6 (SYSCTRL2 0x05) */
|
|
#define AW882XX_HAGCE_START_BIT (6)
|
|
#define AW882XX_HAGCE_BITS_LEN (1)
|
|
#define AW882XX_HAGCE_MASK \
|
|
(~(((1<<AW882XX_HAGCE_BITS_LEN)-1)<<AW882XX_HAGCE_START_BIT))
|
|
|
|
#define AW882XX_HAGCE_DISABLE (0)
|
|
#define AW882XX_HAGCE_DISABLE_VALUE \
|
|
(AW882XX_HAGCE_DISABLE << AW882XX_HAGCE_START_BIT)
|
|
#define AW882XX_HAGCE_ENABLE (1)
|
|
#define AW882XX_HAGCE_ENABLE_VALUE \
|
|
(AW882XX_HAGCE_ENABLE << AW882XX_HAGCE_START_BIT)
|
|
|
|
#define AW882XX_HAGCE_DEFAULT_VALUE (0)
|
|
#define AW882XX_HAGCE_DEFAULT \
|
|
(AW882XX_HAGCE_DEFAULT_VALUE<<AW882XX_HAGCE_START_BIT)
|
|
|
|
/* HDCCE bit 5 (SYSCTRL2 0x05) */
|
|
#define AW882XX_HDCCE_START_BIT (5)
|
|
#define AW882XX_HDCCE_BITS_LEN (1)
|
|
#define AW882XX_HDCCE_MASK \
|
|
(~(((1<<AW882XX_HDCCE_BITS_LEN)-1)<<AW882XX_HDCCE_START_BIT))
|
|
|
|
#define AW882XX_HDCCE_DISABLE (0)
|
|
#define AW882XX_HDCCE_DISABLE_VALUE \
|
|
(AW882XX_HDCCE_DISABLE << AW882XX_HDCCE_START_BIT)
|
|
#define AW882XX_HDCCE_ENABLE (1)
|
|
#define AW882XX_HDCCE_ENABLE_VALUE \
|
|
(AW882XX_HDCCE_ENABLE << AW882XX_HDCCE_START_BIT)
|
|
|
|
#define AW882XX_HDCCE_DEFAULT_VALUE (1)
|
|
#define AW882XX_HDCCE_DEFAULT \
|
|
(AW882XX_HDCCE_DEFAULT_VALUE<<AW882XX_HDCCE_START_BIT)
|
|
|
|
/* HMUTE bit 4 (SYSCTRL2 0x05) */
|
|
#define AW882XX_HMUTE_START_BIT (4)
|
|
#define AW882XX_HMUTE_BITS_LEN (1)
|
|
#define AW882XX_HMUTE_MASK \
|
|
(~(((1<<AW882XX_HMUTE_BITS_LEN)-1)<<AW882XX_HMUTE_START_BIT))
|
|
|
|
#define AW882XX_HMUTE_DISABLE (0)
|
|
#define AW882XX_HMUTE_DISABLE_VALUE \
|
|
(AW882XX_HMUTE_DISABLE << AW882XX_HMUTE_START_BIT)
|
|
#define AW882XX_HMUTE_ENABLE (1)
|
|
#define AW882XX_HMUTE_ENABLE_VALUE \
|
|
(AW882XX_HMUTE_ENABLE << AW882XX_HMUTE_START_BIT)
|
|
|
|
#define AW882XX_HMUTE_DEFAULT_VALUE (1)
|
|
#define AW882XX_HMUTE_DEFAULT \
|
|
(AW882XX_HMUTE_DEFAULT_VALUE<<AW882XX_HMUTE_START_BIT)
|
|
|
|
/* BST_IPEAK bit 3:0 (SYSCTRL2 0x05) */
|
|
#define AW882XX_BST_IPEAK_START_BIT (0)
|
|
#define AW882XX_BST_IPEAK_BITS_LEN (4)
|
|
#define AW882XX_BST_IPEAK_MASK \
|
|
(~(((1<<AW882XX_BST_IPEAK_BITS_LEN)-1)<<AW882XX_BST_IPEAK_START_BIT))
|
|
|
|
#define AW882XX_BST_IPEAK_1P5A (0)
|
|
#define AW882XX_BST_IPEAK_1P5A_VALUE \
|
|
(AW882XX_BST_IPEAK_1P5A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_1P75A (1)
|
|
#define AW882XX_BST_IPEAK_1P75A_VALUE \
|
|
(AW882XX_BST_IPEAK_1P75A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_2P0A (2)
|
|
#define AW882XX_BST_IPEAK_2P0A_VALUE \
|
|
(AW882XX_BST_IPEAK_2P0A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_2P25A (3)
|
|
#define AW882XX_BST_IPEAK_2P25A_VALUE \
|
|
(AW882XX_BST_IPEAK_2P25A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_2P5A (4)
|
|
#define AW882XX_BST_IPEAK_2P5A_VALUE \
|
|
(AW882XX_BST_IPEAK_2P5A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_2P75A (5)
|
|
#define AW882XX_BST_IPEAK_2P75A_VALUE \
|
|
(AW882XX_BST_IPEAK_2P75A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_3P0A (6)
|
|
#define AW882XX_BST_IPEAK_3P0A_VALUE \
|
|
(AW882XX_BST_IPEAK_3P0A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_3P25A (7)
|
|
#define AW882XX_BST_IPEAK_3P25A_VALUE \
|
|
(AW882XX_BST_IPEAK_3P25A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_3P5A (8)
|
|
#define AW882XX_BST_IPEAK_3P5A_VALUE \
|
|
(AW882XX_BST_IPEAK_3P5A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_3P75A (9)
|
|
#define AW882XX_BST_IPEAK_3P75A_VALUE \
|
|
(AW882XX_BST_IPEAK_3P75A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_4A (10)
|
|
#define AW882XX_BST_IPEAK_4A_VALUE \
|
|
(AW882XX_BST_IPEAK_4A << AW882XX_BST_IPEAK_START_BIT)
|
|
#define AW882XX_BST_IPEAK_4P25A (11)
|
|
#define AW882XX_BST_IPEAK_4P25A_VALUE \
|
|
(AW882XX_BST_IPEAK_4P25A << AW882XX_BST_IPEAK_START_BIT)
|
|
|
|
#define AW882XX_BST_IPEAK_DEFAULT_VALUE (8)
|
|
#define AW882XX_BST_IPEAK_DEFAULT \
|
|
(AW882XX_BST_IPEAK_DEFAULT_VALUE<<AW882XX_BST_IPEAK_START_BIT)
|
|
|
|
/* default value of SYSCTRL2 (0x05) */
|
|
/* #define AW882XX_SYSCTRL2_DEFAULT (0x0038) */
|
|
|
|
/* I2SCTRL (0x06) detail */
|
|
/* INPLEV bit 13 (I2SCTRL 0x06) */
|
|
#define AW882XX_INPLEV_START_BIT (13)
|
|
#define AW882XX_INPLEV_BITS_LEN (1)
|
|
#define AW882XX_INPLEV_MASK \
|
|
(~(((1<<AW882XX_INPLEV_BITS_LEN)-1)<<AW882XX_INPLEV_START_BIT))
|
|
|
|
#define AW882XX_INPLEV_NOT_ATTENUATED (0)
|
|
#define AW882XX_INPLEV_NOT_ATTENUATED_VALUE \
|
|
(AW882XX_INPLEV_NOT_ATTENUATED << AW882XX_INPLEV_START_BIT)
|
|
#define AW882XX_INPLEV_ATTENUATED_MINUS_6DB (1)
|
|
#define AW882XX_INPLEV_ATTENUATED_MINUS_6DB_VALUE \
|
|
(AW882XX_INPLEV_ATTENUATED_MINUS_6DB << AW882XX_INPLEV_START_BIT)
|
|
|
|
#define AW882XX_INPLEV_DEFAULT_VALUE (0)
|
|
#define AW882XX_INPLEV_DEFAULT \
|
|
(AW882XX_INPLEV_DEFAULT_VALUE<<AW882XX_INPLEV_START_BIT)
|
|
|
|
/* I2SRXEN bit 12 (I2SCTRL 0x06) */
|
|
#define AW882XX_I2SRXEN_START_BIT (12)
|
|
#define AW882XX_I2SRXEN_BITS_LEN (1)
|
|
#define AW882XX_I2SRXEN_MASK \
|
|
(~(((1<<AW882XX_I2SRXEN_BITS_LEN)-1)<<AW882XX_I2SRXEN_START_BIT))
|
|
|
|
#define AW882XX_I2SRXEN_DISABLE (0)
|
|
#define AW882XX_I2SRXEN_DISABLE_VALUE \
|
|
(AW882XX_I2SRXEN_DISABLE << AW882XX_I2SRXEN_START_BIT)
|
|
#define AW882XX_I2SRXEN_ENABLE (1)
|
|
#define AW882XX_I2SRXEN_ENABLE_VALUE \
|
|
(AW882XX_I2SRXEN_ENABLE << AW882XX_I2SRXEN_START_BIT)
|
|
|
|
#define AW882XX_I2SRXEN_DEFAULT_VALUE (1)
|
|
#define AW882XX_I2SRXEN_DEFAULT \
|
|
(AW882XX_I2SRXEN_DEFAULT_VALUE<<AW882XX_I2SRXEN_START_BIT)
|
|
|
|
/* CHSEL bit 11:10 (I2SCTRL 0x06) */
|
|
#define AW882XX_CHSEL_START_BIT (10)
|
|
#define AW882XX_CHSEL_BITS_LEN (2)
|
|
#define AW882XX_CHSEL_MASK \
|
|
(~(((1<<AW882XX_CHSEL_BITS_LEN)-1)<<AW882XX_CHSEL_START_BIT))
|
|
|
|
#define AW882XX_CHSEL_RESERVED (0)
|
|
#define AW882XX_CHSEL_RESERVED_VALUE \
|
|
(AW882XX_CHSEL_RESERVED << AW882XX_CHSEL_START_BIT)
|
|
#define AW882XX_CHSEL_LEFT (1)
|
|
#define AW882XX_CHSEL_LEFT_VALUE \
|
|
(AW882XX_CHSEL_LEFT << AW882XX_CHSEL_START_BIT)
|
|
#define AW882XX_CHSEL_RIGHT (2)
|
|
#define AW882XX_CHSEL_RIGHT_VALUE \
|
|
(AW882XX_CHSEL_RIGHT << AW882XX_CHSEL_START_BIT)
|
|
#define AW882XX_CHSEL_MONO_LR2 (3)
|
|
#define AW882XX_CHSEL_MONO_LR2_VALUE \
|
|
(AW882XX_CHSEL_MONO_LR2 << AW882XX_CHSEL_START_BIT)
|
|
|
|
#define AW882XX_CHSEL_DEFAULT_VALUE (1)
|
|
#define AW882XX_CHSEL_DEFAULT \
|
|
(AW882XX_CHSEL_DEFAULT_VALUE<<AW882XX_CHSEL_START_BIT)
|
|
|
|
/* I2SMD bit 9:8 (I2SCTRL 0x06) */
|
|
#define AW882XX_I2SMD_START_BIT (8)
|
|
#define AW882XX_I2SMD_BITS_LEN (2)
|
|
#define AW882XX_I2SMD_MASK \
|
|
(~(((1<<AW882XX_I2SMD_BITS_LEN)-1)<<AW882XX_I2SMD_START_BIT))
|
|
|
|
#define AW882XX_I2SMD_STANDARD_I2S (0)
|
|
#define AW882XX_I2SMD_STANDARD_I2S_VALUE \
|
|
(AW882XX_I2SMD_STANDARD_I2S << AW882XX_I2SMD_START_BIT)
|
|
#define AW882XX_I2SMD_MSB_JUSTIFIED (1)
|
|
#define AW882XX_I2SMD_MSB_JUSTIFIED_VALUE \
|
|
(AW882XX_I2SMD_MSB_JUSTIFIED << AW882XX_I2SMD_START_BIT)
|
|
#define AW882XX_I2SMD_LSB_JUSTIFIED (2)
|
|
#define AW882XX_I2SMD_LSB_JUSTIFIED_VALUE \
|
|
(AW882XX_I2SMD_LSB_JUSTIFIED << AW882XX_I2SMD_START_BIT)
|
|
#define AW882XX_I2SMD_RESERVED (3)
|
|
#define AW882XX_I2SMD_RESERVED_VALUE \
|
|
(AW882XX_I2SMD_RESERVED << AW882XX_I2SMD_START_BIT)
|
|
|
|
#define AW882XX_I2SMD_DEFAULT_VALUE (0)
|
|
#define AW882XX_I2SMD_DEFAULT \
|
|
(AW882XX_I2SMD_DEFAULT_VALUE<<AW882XX_I2SMD_START_BIT)
|
|
|
|
/* I2SFS bit 7:6 (I2SCTRL 0x06) */
|
|
#define AW882XX_I2SFS_START_BIT (6)
|
|
#define AW882XX_I2SFS_BITS_LEN (2)
|
|
#define AW882XX_I2SFS_MASK \
|
|
(~(((1<<AW882XX_I2SFS_BITS_LEN)-1)<<AW882XX_I2SFS_START_BIT))
|
|
|
|
#define AW882XX_I2SFS_16_BITS (0)
|
|
#define AW882XX_I2SFS_16_BITS_VALUE \
|
|
(AW882XX_I2SFS_16_BITS << AW882XX_I2SFS_START_BIT)
|
|
#define AW882XX_I2SFS_20_BITS (1)
|
|
#define AW882XX_I2SFS_20_BITS_VALUE \
|
|
(AW882XX_I2SFS_20_BITS << AW882XX_I2SFS_START_BIT)
|
|
#define AW882XX_I2SFS_24_BITS (2)
|
|
#define AW882XX_I2SFS_24_BITS_VALUE \
|
|
(AW882XX_I2SFS_24_BITS << AW882XX_I2SFS_START_BIT)
|
|
#define AW882XX_I2SFS_32_BITS (3)
|
|
#define AW882XX_I2SFS_32_BITS_VALUE \
|
|
(AW882XX_I2SFS_32_BITS << AW882XX_I2SFS_START_BIT)
|
|
|
|
#define AW882XX_I2SFS_DEFAULT_VALUE (3)
|
|
#define AW882XX_I2SFS_DEFAULT \
|
|
(AW882XX_I2SFS_DEFAULT_VALUE<<AW882XX_I2SFS_START_BIT)
|
|
|
|
/* I2SBCK bit 5:4 (I2SCTRL 0x06) */
|
|
#define AW882XX_I2SBCK_START_BIT (4)
|
|
#define AW882XX_I2SBCK_BITS_LEN (2)
|
|
#define AW882XX_I2SBCK_MASK \
|
|
(~(((1<<AW882XX_I2SBCK_BITS_LEN)-1)<<AW882XX_I2SBCK_START_BIT))
|
|
|
|
#define AW882XX_I2SBCK_32FS (0)
|
|
#define AW882XX_I2SBCK_32FS_VALUE \
|
|
(AW882XX_I2SBCK_32FS << AW882XX_I2SBCK_START_BIT)
|
|
#define AW882XX_I2SBCK_48FS (1)
|
|
#define AW882XX_I2SBCK_48FS_VALUE \
|
|
(AW882XX_I2SBCK_48FS << AW882XX_I2SBCK_START_BIT)
|
|
#define AW882XX_I2SBCK_64FS (2)
|
|
#define AW882XX_I2SBCK_64FS_VALUE \
|
|
(AW882XX_I2SBCK_64FS << AW882XX_I2SBCK_START_BIT)
|
|
#define AW882XX_I2SBCK_RESERVED (3)
|
|
#define AW882XX_I2SBCK_RESERVED_VALUE \
|
|
(AW882XX_I2SBCK_RESERVED << AW882XX_I2SBCK_START_BIT)
|
|
|
|
#define AW882XX_I2SBCK_DEFAULT_VALUE (2)
|
|
#define AW882XX_I2SBCK_DEFAULT \
|
|
(AW882XX_I2SBCK_DEFAULT_VALUE<<AW882XX_I2SBCK_START_BIT)
|
|
|
|
/* I2SSR bit 3:0 (I2SCTRL 0x06) */
|
|
#define AW882XX_I2SSR_START_BIT (0)
|
|
#define AW882XX_I2SSR_BITS_LEN (4)
|
|
#define AW882XX_I2SSR_MASK \
|
|
(~(((1<<AW882XX_I2SSR_BITS_LEN)-1)<<AW882XX_I2SSR_START_BIT))
|
|
|
|
/* I2S CCO_UMX */
|
|
#define AW882XX_I2S_CCO_MUX_START_BIT (14)
|
|
#define AW882XX_I2S_CCO_MUX_BITS_LEN (1)
|
|
#define AW882XX_I2S_CCO_MUX_MASK \
|
|
(~(((1<<AW882XX_I2S_CCO_MUX_BITS_LEN)-1)<<AW882XX_I2S_CCO_MUX_START_BIT))
|
|
|
|
#define AW882XX_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE (0)
|
|
#define AW882XX_I2S_CCO_MUX_8_16_32KHZ_VALUE \
|
|
(AW882XX_I2S_CCO_MUX_8_16_32KHZ_BIT_VALUE<<AW882XX_I2S_CCO_MUX_START_BIT)
|
|
|
|
#define AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE (1)
|
|
#define AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_VALUE \
|
|
(AW882XX_I2S_CCO_MUX_EXC_8_16_32KHZ_BIT_VALUE<<AW882XX_I2S_CCO_MUX_START_BIT)
|
|
|
|
#define AW882XX_I2SSR_8KHZ (0)
|
|
#define AW882XX_I2SSR_8KHZ_VALUE \
|
|
(AW882XX_I2SSR_8KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_11P025KHZ (1)
|
|
#define AW882XX_I2SSR_11P025KHZ_VALUE \
|
|
(AW882XX_I2SSR_11P025KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_12KHZ (2)
|
|
#define AW882XX_I2SSR_12KHZ_VALUE \
|
|
(AW882XX_I2SSR_12KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_16KHZ (3)
|
|
#define AW882XX_I2SSR_16KHZ_VALUE \
|
|
(AW882XX_I2SSR_16KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_22P05KHZ (4)
|
|
#define AW882XX_I2SSR_22P05KHZ_VALUE \
|
|
(AW882XX_I2SSR_22P05KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_24KHZ (5)
|
|
#define AW882XX_I2SSR_24KHZ_VALUE \
|
|
(AW882XX_I2SSR_24KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_32KHZ (6)
|
|
#define AW882XX_I2SSR_32KHZ_VALUE \
|
|
(AW882XX_I2SSR_32KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_44P1KHZ (7)
|
|
#define AW882XX_I2SSR_44P1KHZ_VALUE \
|
|
(AW882XX_I2SSR_44P1KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_48KHZ (8)
|
|
#define AW882XX_I2SSR_48KHZ_VALUE \
|
|
(AW882XX_I2SSR_48KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_96KHZ (9)
|
|
#define AW882XX_I2SSR_96KHZ_VALUE \
|
|
(AW882XX_I2SSR_96KHZ << AW882XX_I2SSR_START_BIT)
|
|
#define AW882XX_I2SSR_192KHZ (10)
|
|
#define AW882XX_I2SSR_192KHZ_VALUE \
|
|
(AW882XX_I2SSR_192KHZ << AW882XX_I2SSR_START_BIT)
|
|
|
|
#define AW882XX_I2SSR_DEFAULT_VALUE (8)
|
|
#define AW882XX_I2SSR_DEFAULT \
|
|
(AW882XX_I2SSR_DEFAULT_VALUE<<AW882XX_I2SSR_START_BIT)
|
|
|
|
/* default value of I2SCTRL (0x06) */
|
|
/* #define AW882XX_I2SCTRL_DEFAULT (0x14E8) */
|
|
|
|
/* I2SCFG1 (0x07) detail */
|
|
/* I2S_TX_SLOTVLD bit 13:12 (I2SCFG1 0x07) */
|
|
#define AW882XX_I2S_TX_SLOTVLD_START_BIT (12)
|
|
#define AW882XX_I2S_TX_SLOTVLD_BITS_LEN (2)
|
|
#define AW882XX_I2S_TX_SLOTVLD_MASK \
|
|
(~(((1<<AW882XX_I2S_TX_SLOTVLD_BITS_LEN)-1)<< \
|
|
AW882XX_I2S_TX_SLOTVLD_START_BIT))
|
|
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_0 (0)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_0_VALUE \
|
|
(AW882XX_I2S_TX_SLOTVLD_SLOT_0 << AW882XX_I2S_TX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_1 (1)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_1_VALUE \
|
|
(AW882XX_I2S_TX_SLOTVLD_SLOT_1 << AW882XX_I2S_TX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_2 (2)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_2_VALUE \
|
|
(AW882XX_I2S_TX_SLOTVLD_SLOT_2 << AW882XX_I2S_TX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_3 (3)
|
|
#define AW882XX_I2S_TX_SLOTVLD_SLOT_3_VALUE \
|
|
(AW882XX_I2S_TX_SLOTVLD_SLOT_3 << AW882XX_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
#define AW882XX_I2S_TX_SLOTVLD_DEFAULT_VALUE (0)
|
|
#define AW882XX_I2S_TX_SLOTVLD_DEFAULT \
|
|
(AW882XX_I2S_TX_SLOTVLD_DEFAULT_VALUE<<AW882XX_I2S_TX_SLOTVLD_START_BIT)
|
|
|
|
/* I2S_RX_SLOTVLD bit 11:8 (I2SCFG1 0x07) */
|
|
#define AW882XX_I2S_RX_SLOTVLD_START_BIT (8)
|
|
#define AW882XX_I2S_RX_SLOTVLD_BITS_LEN (4)
|
|
#define AW882XX_I2S_RX_SLOTVLD_MASK \
|
|
(~(((1<<AW882XX_I2S_RX_SLOTVLD_BITS_LEN)-1)<< \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT))
|
|
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_1 (3)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_1_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_1 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_2 (5)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_2_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_2 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_2 (6)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_2_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_2 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_3 (9)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_3_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_0_AND_3 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_3 (10)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_3_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_1_AND_3 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_2_AND_3 (12)
|
|
#define AW882XX_I2S_RX_SLOTVLD_SLOTS_2_AND_3_VALUE \
|
|
(AW882XX_I2S_RX_SLOTVLD_SLOTS_2_AND_3 << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
|
|
#define AW882XX_I2S_RX_SLOTVLD_DEFAULT_VALUE (3)
|
|
#define AW882XX_I2S_RX_SLOTVLD_DEFAULT \
|
|
(AW882XX_I2S_RX_SLOTVLD_DEFAULT_VALUE << \
|
|
AW882XX_I2S_RX_SLOTVLD_START_BIT)
|
|
|
|
/* CFSEL bit 7:6 (I2SCFG1 0x07) */
|
|
#define AW882XX_CFSEL_START_BIT (6)
|
|
#define AW882XX_CFSEL_BITS_LEN (2)
|
|
#define AW882XX_CFSEL_MASK \
|
|
(~(((1<<AW882XX_CFSEL_BITS_LEN)-1)<<AW882XX_CFSEL_START_BIT))
|
|
|
|
#define AW882XX_CFSEL_HAGC_DATA (0)
|
|
#define AW882XX_CFSEL_HAGC_DATA_VALUE \
|
|
(AW882XX_CFSEL_HAGC_DATA << AW882XX_CFSEL_START_BIT)
|
|
#define AW882XX_CFSEL_IV_SENSE_DATA (1)
|
|
#define AW882XX_CFSEL_IV_SENSE_DATA_VALUE \
|
|
(AW882XX_CFSEL_IV_SENSE_DATA << AW882XX_CFSEL_START_BIT)
|
|
#define AW882XX_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES (2)
|
|
#define AW882XX_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES_VALUE \
|
|
(AW882XX_CFSEL_IVT_DATA_MAPPING_ACCORDING_TO_I2S_AUDIO_RES << \
|
|
AW882XX_CFSEL_START_BIT)
|
|
#define AW882XX_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC (3)
|
|
#define AW882XX_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC_VALUE \
|
|
(AW882XX_CFSEL_IVT_DATA_MAPPING_AS__I_PVDD_VBAT_V_T_SYNC << \
|
|
AW882XX_CFSEL_START_BIT)
|
|
|
|
#define AW882XX_CFSEL_DEFAULT_VALUE (0)
|
|
#define AW882XX_CFSEL_DEFAULT \
|
|
(AW882XX_CFSEL_DEFAULT_VALUE<<AW882XX_CFSEL_START_BIT)
|
|
|
|
/* DRVSTREN bit 5 (I2SCFG1 0x07) */
|
|
#define AW882XX_DRVSTREN_START_BIT (5)
|
|
#define AW882XX_DRVSTREN_BITS_LEN (1)
|
|
#define AW882XX_DRVSTREN_MASK \
|
|
(~(((1<<AW882XX_DRVSTREN_BITS_LEN)-1)<<AW882XX_DRVSTREN_START_BIT))
|
|
|
|
#define AW882XX_DRVSTREN_2MA (0)
|
|
#define AW882XX_DRVSTREN_2MA_VALUE \
|
|
(AW882XX_DRVSTREN_2MA << AW882XX_DRVSTREN_START_BIT)
|
|
#define AW882XX_DRVSTREN_8MA (1)
|
|
#define AW882XX_DRVSTREN_8MA_VALUE \
|
|
(AW882XX_DRVSTREN_8MA << AW882XX_DRVSTREN_START_BIT)
|
|
|
|
#define AW882XX_DRVSTREN_DEFAULT_VALUE (1)
|
|
#define AW882XX_DRVSTREN_DEFAULT \
|
|
(AW882XX_DRVSTREN_DEFAULT_VALUE<<AW882XX_DRVSTREN_START_BIT)
|
|
|
|
/* DOHZ bit 4 (I2SCFG1 0x07) */
|
|
#define AW882XX_DOHZ_START_BIT (4)
|
|
#define AW882XX_DOHZ_BITS_LEN (1)
|
|
#define AW882XX_DOHZ_MASK \
|
|
(~(((1<<AW882XX_DOHZ_BITS_LEN)-1)<<AW882XX_DOHZ_START_BIT))
|
|
|
|
#define AW882XX_DOHZ_ALL_AVAILABLE (0)
|
|
#define AW882XX_DOHZ_ALL_AVAILABLE_VALUE \
|
|
(AW882XX_DOHZ_ALL_AVAILABLE << AW882XX_DOHZ_START_BIT)
|
|
#define AW882XX_DOHZ_HIZ (1)
|
|
#define AW882XX_DOHZ_HIZ_VALUE \
|
|
(AW882XX_DOHZ_HIZ << AW882XX_DOHZ_START_BIT)
|
|
|
|
#define AW882XX_DOHZ_DEFAULT_VALUE (1)
|
|
#define AW882XX_DOHZ_DEFAULT \
|
|
(AW882XX_DOHZ_DEFAULT_VALUE<<AW882XX_DOHZ_START_BIT)
|
|
|
|
/* FSYNC_TYPE bit 3 (I2SCFG1 0x07) */
|
|
#define AW882XX_FSYNC_TYPE_START_BIT (3)
|
|
#define AW882XX_FSYNC_TYPE_BITS_LEN (1)
|
|
#define AW882XX_FSYNC_TYPE_MASK \
|
|
(~(((1<<AW882XX_FSYNC_TYPE_BITS_LEN)-1)<<AW882XX_FSYNC_TYPE_START_BIT))
|
|
|
|
#define AW882XX_FSYNC_TYPE_ONE_SLOT (0)
|
|
#define AW882XX_FSYNC_TYPE_ONE_SLOT_VALUE \
|
|
(AW882XX_FSYNC_TYPE_ONE_SLOT << AW882XX_FSYNC_TYPE_START_BIT)
|
|
#define AW882XX_FSYNC_TYPE_ONE_BCK (1)
|
|
#define AW882XX_FSYNC_TYPE_ONE_BCK_VALUE \
|
|
(AW882XX_FSYNC_TYPE_ONE_BCK << AW882XX_FSYNC_TYPE_START_BIT)
|
|
|
|
#define AW882XX_FSYNC_TYPE_DEFAULT_VALUE (0)
|
|
#define AW882XX_FSYNC_TYPE_DEFAULT \
|
|
(AW882XX_FSYNC_TYPE_DEFAULT_VALUE<<AW882XX_FSYNC_TYPE_START_BIT)
|
|
|
|
/* SLOT_NUM bit 2 (I2SCFG1 0x07) */
|
|
#define AW882XX_SLOT_NUM_START_BIT (2)
|
|
#define AW882XX_SLOT_NUM_BITS_LEN (1)
|
|
#define AW882XX_SLOT_NUM_MASK \
|
|
(~(((1<<AW882XX_SLOT_NUM_BITS_LEN)-1)<<AW882XX_SLOT_NUM_START_BIT))
|
|
|
|
#define AW882XX_SLOT_NUM_2_SLOTS (0)
|
|
#define AW882XX_SLOT_NUM_2_SLOTS_VALUE \
|
|
(AW882XX_SLOT_NUM_2_SLOTS << AW882XX_SLOT_NUM_START_BIT)
|
|
#define AW882XX_SLOT_NUM_4_SLOTS (1)
|
|
#define AW882XX_SLOT_NUM_4_SLOTS_VALUE \
|
|
(AW882XX_SLOT_NUM_4_SLOTS << AW882XX_SLOT_NUM_START_BIT)
|
|
|
|
#define AW882XX_SLOT_NUM_DEFAULT_VALUE (0)
|
|
#define AW882XX_SLOT_NUM_DEFAULT \
|
|
(AW882XX_SLOT_NUM_DEFAULT_VALUE<<AW882XX_SLOT_NUM_START_BIT)
|
|
|
|
/* I2SCHS bit 1 (I2SCFG1 0x07) */
|
|
#define AW882XX_I2SCHS_START_BIT (1)
|
|
#define AW882XX_I2SCHS_BITS_LEN (1)
|
|
#define AW882XX_I2SCHS_MASK \
|
|
(~(((1<<AW882XX_I2SCHS_BITS_LEN)-1)<<AW882XX_I2SCHS_START_BIT))
|
|
|
|
#define AW882XX_I2SCHS_LEFT_CHANNEL (0)
|
|
#define AW882XX_I2SCHS_LEFT_CHANNEL_VALUE \
|
|
(AW882XX_I2SCHS_LEFT_CHANNEL << AW882XX_I2SCHS_START_BIT)
|
|
#define AW882XX_I2SCHS_RIGHT_CHANNEL (1)
|
|
#define AW882XX_I2SCHS_RIGHT_CHANNEL_VALUE \
|
|
(AW882XX_I2SCHS_RIGHT_CHANNEL << AW882XX_I2SCHS_START_BIT)
|
|
|
|
#define AW882XX_I2SCHS_DEFAULT_VALUE (0)
|
|
#define AW882XX_I2SCHS_DEFAULT \
|
|
(AW882XX_I2SCHS_DEFAULT_VALUE<<AW882XX_I2SCHS_START_BIT)
|
|
|
|
/* I2STXEN bit 0 (I2SCFG1 0x07) */
|
|
#define AW882XX_I2STXEN_START_BIT (0)
|
|
#define AW882XX_I2STXEN_BITS_LEN (1)
|
|
#define AW882XX_I2STXEN_MASK \
|
|
(~(((1<<AW882XX_I2STXEN_BITS_LEN)-1)<<AW882XX_I2STXEN_START_BIT))
|
|
|
|
#define AW882XX_I2STXEN_DISABLE (0)
|
|
#define AW882XX_I2STXEN_DISABLE_VALUE \
|
|
(AW882XX_I2STXEN_DISABLE << AW882XX_I2STXEN_START_BIT)
|
|
#define AW882XX_I2STXEN_ENABLE (1)
|
|
#define AW882XX_I2STXEN_ENABLE_VALUE \
|
|
(AW882XX_I2STXEN_ENABLE << AW882XX_I2STXEN_START_BIT)
|
|
|
|
#define AW882XX_I2STXEN_DEFAULT_VALUE (0)
|
|
#define AW882XX_I2STXEN_DEFAULT \
|
|
(AW882XX_I2STXEN_DEFAULT_VALUE<<AW882XX_I2STXEN_START_BIT)
|
|
|
|
/* default value of I2SCFG1 (0x07) */
|
|
/* #define AW882XX_I2SCFG1_DEFAULT (0x0330) */
|
|
|
|
/* I2SCFG2 (0x08) detail */
|
|
/* RX_FLS bit 15 (I2SCFG2 0x08) */
|
|
#define AW882XX_RX_FLS_START_BIT (15)
|
|
#define AW882XX_RX_FLS_BITS_LEN (1)
|
|
#define AW882XX_RX_FLS_MASK \
|
|
(~(((1<<AW882XX_RX_FLS_BITS_LEN)-1)<<AW882XX_RX_FLS_START_BIT))
|
|
|
|
#define AW882XX_RX_FLS_NORMAL_WORK_MODE (0)
|
|
#define AW882XX_RX_FLS_NORMAL_WORK_MODE_VALUE \
|
|
(AW882XX_RX_FLS_NORMAL_WORK_MODE << AW882XX_RX_FLS_START_BIT)
|
|
#define AW882XX_RX_FLS_FLUSH_FIFO (1)
|
|
#define AW882XX_RX_FLS_FLUSH_FIFO_VALUE \
|
|
(AW882XX_RX_FLS_FLUSH_FIFO << AW882XX_RX_FLS_START_BIT)
|
|
|
|
#define AW882XX_RX_FLS_DEFAULT_VALUE (0)
|
|
#define AW882XX_RX_FLS_DEFAULT \
|
|
(AW882XX_RX_FLS_DEFAULT_VALUE<<AW882XX_RX_FLS_START_BIT)
|
|
|
|
/* RX_THRS bit 13:12 (I2SCFG2 0x08) */
|
|
#define AW882XX_RX_THRS_START_BIT (12)
|
|
#define AW882XX_RX_THRS_BITS_LEN (2)
|
|
#define AW882XX_RX_THRS_MASK \
|
|
(~(((1<<AW882XX_RX_THRS_BITS_LEN)-1)<<AW882XX_RX_THRS_START_BIT))
|
|
|
|
#define AW882XX_RX_THRS_DEFAULT_VALUE (2)
|
|
#define AW882XX_RX_THRS_DEFAULT \
|
|
(AW882XX_RX_THRS_DEFAULT_VALUE<<AW882XX_RX_THRS_START_BIT)
|
|
|
|
/* TX_FLS bit 11 (I2SCFG2 0x08) */
|
|
#define AW882XX_TX_FLS_START_BIT (11)
|
|
#define AW882XX_TX_FLS_BITS_LEN (1)
|
|
#define AW882XX_TX_FLS_MASK \
|
|
(~(((1<<AW882XX_TX_FLS_BITS_LEN)-1)<<AW882XX_TX_FLS_START_BIT))
|
|
|
|
#define AW882XX_TX_FLS_NORMAL_WORK_MODE (0)
|
|
#define AW882XX_TX_FLS_NORMAL_WORK_MODE_VALUE \
|
|
(AW882XX_TX_FLS_NORMAL_WORK_MODE << AW882XX_TX_FLS_START_BIT)
|
|
#define AW882XX_TX_FLS_FLUSH_FIFO (1)
|
|
#define AW882XX_TX_FLS_FLUSH_FIFO_VALUE \
|
|
(AW882XX_TX_FLS_FLUSH_FIFO << AW882XX_TX_FLS_START_BIT)
|
|
|
|
#define AW882XX_TX_FLS_DEFAULT_VALUE (0)
|
|
#define AW882XX_TX_FLS_DEFAULT \
|
|
(AW882XX_TX_FLS_DEFAULT_VALUE<<AW882XX_TX_FLS_START_BIT)
|
|
|
|
/* TX_THRS bit 9:8 (I2SCFG2 0x08) */
|
|
#define AW882XX_TX_THRS_START_BIT (8)
|
|
#define AW882XX_TX_THRS_BITS_LEN (2)
|
|
#define AW882XX_TX_THRS_MASK \
|
|
(~(((1<<AW882XX_TX_THRS_BITS_LEN)-1)<<AW882XX_TX_THRS_START_BIT))
|
|
|
|
#define AW882XX_TX_THRS_DEFAULT_VALUE (1)
|
|
#define AW882XX_TX_THRS_DEFAULT \
|
|
(AW882XX_TX_THRS_DEFAULT_VALUE<<AW882XX_TX_THRS_START_BIT)
|
|
|
|
/* VDSEL bit 3 (I2SCFG2 0x08) */
|
|
#define AW882XX_VDSEL_START_BIT (3)
|
|
#define AW882XX_VDSEL_BITS_LEN (1)
|
|
#define AW882XX_VDSEL_MASK \
|
|
(~(((1<<AW882XX_VDSEL_BITS_LEN)-1)<<AW882XX_VDSEL_START_BIT))
|
|
|
|
#define AW882XX_VDSEL_DAC_DATA (0)
|
|
#define AW882XX_VDSEL_DAC_DATA_VALUE \
|
|
(AW882XX_VDSEL_DAC_DATA << AW882XX_VDSEL_START_BIT)
|
|
#define AW882XX_VDSEL_VSENSE_DATA (1)
|
|
#define AW882XX_VDSEL_VSENSE_DATA_VALUE \
|
|
(AW882XX_VDSEL_VSENSE_DATA << AW882XX_VDSEL_START_BIT)
|
|
|
|
#define AW882XX_VDSEL_DEFAULT_VALUE (0)
|
|
#define AW882XX_VDSEL_DEFAULT \
|
|
(AW882XX_VDSEL_DEFAULT_VALUE<<AW882XX_VDSEL_START_BIT)
|
|
|
|
/* IV2CH bit 2 (I2SCFG2 0x08) */
|
|
#define AW882XX_IV2CH_START_BIT (2)
|
|
#define AW882XX_IV2CH_BITS_LEN (1)
|
|
#define AW882XX_IV2CH_MASK \
|
|
(~(((1<<AW882XX_IV2CH_BITS_LEN)-1)<<AW882XX_IV2CH_START_BIT))
|
|
|
|
#define AW882XX_IV2CH_LEGACY_MODE (0)
|
|
#define AW882XX_IV2CH_LEGACY_MODE_VALUE \
|
|
(AW882XX_IV2CH_LEGACY_MODE << AW882XX_IV2CH_START_BIT)
|
|
#define AW882XX_IV2CH_16BITS_PER_CHANNEL (1)
|
|
#define AW882XX_IV2CH_16BITS_PER_CHANNEL_VALUE \
|
|
(AW882XX_IV2CH_16BITS_PER_CHANNEL << AW882XX_IV2CH_START_BIT)
|
|
|
|
#define AW882XX_IV2CH_DEFAULT_VALUE (0)
|
|
#define AW882XX_IV2CH_DEFAULT \
|
|
(AW882XX_IV2CH_DEFAULT_VALUE<<AW882XX_IV2CH_START_BIT)
|
|
|
|
/* default value of I2SCFG2 (0x08) */
|
|
/* #define AW882XX_I2SCFG2_DEFAULT (0x2100) */
|
|
|
|
|
|
/* HAGCCFG4 (0x0C) detail */
|
|
/* VOL bit 15:8 (HAGCCFG4 0x0C) */
|
|
#define AW882XX_VOL_START_BIT (8)
|
|
#define AW882XX_VOL_BITS_LEN (8)
|
|
#define AW882XX_VOL_MASK \
|
|
(~(((1<<AW882XX_VOL_BITS_LEN)-1)<<AW882XX_VOL_START_BIT))
|
|
|
|
#define AW882XX_VOLUME_MAX (0)
|
|
#define AW882XX_VOLUME_MIN (-255)
|
|
|
|
#define AW882XX_VOL_DEFAULT_VALUE (0)
|
|
#define AW882XX_VOL_DEFAULT \
|
|
(AW882XX_VOL_DEFAULT_VALUE<<AW882XX_VOL_START_BIT)
|
|
|
|
/* HOLDTH bit 7:0 (HAGCCFG4 0x0C) */
|
|
#define AW882XX_HOLDTH_START_BIT (0)
|
|
#define AW882XX_HOLDTH_BITS_LEN (8)
|
|
#define AW882XX_HOLDTH_MASK \
|
|
(~(((1<<AW882XX_HOLDTH_BITS_LEN)-1)<<AW882XX_HOLDTH_START_BIT))
|
|
|
|
#define AW882XX_HOLDTH_RESERVED (0)
|
|
#define AW882XX_HOLDTH_RESERVED_VALUE \
|
|
(AW882XX_HOLDTH_RESERVED << AW882XX_HOLDTH_START_BIT)
|
|
|
|
#define AW882XX_HOLDTH_DEFAULT_VALUE (0x64)
|
|
#define AW882XX_HOLDTH_DEFAULT \
|
|
(AW882XX_HOLDTH_DEFAULT_VALUE<<AW882XX_HOLDTH_START_BIT)
|
|
|
|
/* default value of HAGCCFG4 (0x0C) */
|
|
/* #define AW882XX_HAGCCFG4_DEFAULT (0x0064) */
|
|
|
|
/* #define AW882XX_TESTDET_DEFAULT (0x0000) */
|
|
|
|
|
|
/********************************************
|
|
* Vcalb
|
|
*******************************************/
|
|
#define AW882XX_EF_VSN_GESLP_MASK (0x03ff)
|
|
#define AW882XX_EF_VSN_GESLP_SIGN_MASK (0x0200)
|
|
#define AW882XX_EF_VSN_GESLP_NEG (0xfc00)
|
|
|
|
#define AW882XX_EF_ISN_GESLP_MASK (0x03ff)
|
|
#define AW882XX_EF_ISN_GESLP_SIGN_MASK (0x0200)
|
|
#define AW882XX_EF_ISN_GESLP_NEG (0xfc00)
|
|
|
|
#define AW882XX_CABL_BASE_VALUE (1000)
|
|
#define AW882XX_ICABLK_FACTOR (1)
|
|
#define AW882XX_VCABLK_FACTOR (1)
|
|
|
|
#define AW882XX_VCAL_FACTOR (1<<13)
|
|
|
|
#endif /* #ifndef __AW882XX_REG_H__ */
|