Jilai Wang
4d0115c8c0
This change is to correct the property from "qcom,qcom,npu-dsp-sid-mapped" to "qcom,npu-dsp-sid-mapped". Change-Id: I96c0f8c8cd463e14e4112d50fb9ea47c733c7580
274 lines
5.5 KiB
Devicetree
274 lines
5.5 KiB
Devicetree
&soc {
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msm_npu: qcom,msm_npu@9800000 {
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compatible = "qcom,msm-npu";
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status = "ok"
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reg = <0x9900000 0x20000>,
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<0x99F0000 0x10000>,
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<0x9980000 0x10000>,
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<0x17c00000 0x10000>,
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<0x01F40000 0x40000>,
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<0x780000 0x7000>;
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reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
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"qfprom_physical";
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interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
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"general_irq";
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iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>,
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<&apps_smmu 0x1881 0x400>, <&apps_smmu 0x1882 0x400>;
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qcom,npu-dsp-sid-mapped;
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clocks = <&npucc NPU_CC_XO_CLK>,
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<&npucc NPU_CC_CORE_CLK>,
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<&npucc NPU_CC_CAL_HM0_CLK>,
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<&npucc NPU_CC_CAL_HM0_CDC_CLK>,
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<&npucc NPU_CC_NOC_AXI_CLK>,
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<&npucc NPU_CC_NOC_AHB_CLK>,
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<&npucc NPU_CC_NOC_DMA_CLK>,
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<&npucc NPU_CC_LLM_CLK>,
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<&npucc NPU_CC_LLM_XO_CLK>,
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<&npucc NPU_CC_LLM_TEMP_CLK>,
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<&npucc NPU_CC_LLM_CURR_CLK>,
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<&npucc NPU_CC_DL_LLM_CLK>,
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<&npucc NPU_CC_ISENSE_CLK>,
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<&npucc NPU_CC_DPM_CLK>,
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<&npucc NPU_CC_DPM_XO_CLK>,
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<&npucc NPU_CC_DL_DPM_CLK>,
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<&npucc NPU_CC_RSC_XO_CLK>,
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<&npucc NPU_CC_DPM_TEMP_CLK>,
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<&npucc NPU_CC_CAL_HM0_DPM_IP_CLK>,
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<&npucc NPU_CC_S2P_CLK>,
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<&npucc NPU_CC_BWMON_CLK>,
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<&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
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<&npucc NPU_CC_BTO_CORE_CLK>,
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<&npucc NPU_DSP_CORE_CLK_SRC>;
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clock-names = "xo_clk",
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"npu_core_clk",
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"cal_hm0_clk",
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"cal_hm0_cdc_clk",
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"axi_clk",
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"ahb_clk",
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"dma_clk",
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"llm_clk",
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"llm_xo_clk",
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"llm_temp_clk",
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"llm_curr_clk",
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"dl_llm_clk",
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"isense_clk",
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"dpm_clk",
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"dpm_xo_clk",
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"dl_dpm_clk",
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"rsc_xo_clk",
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"dpm_temp_clk",
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"cal_hm0_dpm_ip_clk",
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"s2p_clk",
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"bwmon_clk",
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"cal_hm0_perf_cnt_clk",
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"bto_core_clk",
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"dsp_core_clk_src";
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vdd-supply = <&npu_core_gdsc>;
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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qcom,proxy-reg-names ="vdd", "vdd_cx";
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qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
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resets = <&npucc NPU_CC_DPM_TEMP_CLK_ARES>,
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<&npucc NPU_CC_LLM_CURR_CLK_ARES>,
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<&npucc NPU_CC_LLM_TEMP_CLK_ARES>;
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reset-names = "dpm_temp_clk", "llm_curr_clk", "llm_temp_clk";
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#cooling-cells = <2>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
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IPCC_MPROC_SIGNAL_GLINK_QMP>,
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<&ipcc_mproc IPCC_CLIENT_NPU
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IPCC_MPROC_SIGNAL_SMP2P>,
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<&ipcc_mproc IPCC_CLIENT_NPU
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IPCC_MPROC_SIGNAL_PING>;
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mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
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#mbox-cells = <2>;
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qcom,npubw-devs = <&npu_npu_llcc_bw &npu_llcc_ddr_bw &npudsp_npu_ddr_bw>;
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qcom,npubw-dev-names = "npu_llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw";
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qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
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<MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
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qcom,npu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,npu-pwrlevels";
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initial-pwrlevel = <5>;
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qcom,npu-pwrlevel@0 {
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reg = <0>;
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vreg = <1>;
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clk-freq = <19200000
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100000000
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230000000
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230000000
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150000000
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40000000
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300000000
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100000000
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19200000
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50000000
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50000000
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100000000
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100000000
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100000000
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19200000
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100000000
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19200000
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50000000
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230000000
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50000000
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19200000
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230000000
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19200000
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300000000>;
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};
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qcom,npu-pwrlevel@1 {
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reg = <1>;
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vreg = <2>;
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clk-freq = <19200000
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200000000
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422000000
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422000000
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207000000
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40000000
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403000000
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200000000
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19200000
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50000000
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50000000
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200000000
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200000000
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200000000
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19200000
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200000000
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19200000
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50000000
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422000000
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50000000
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19200000
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422000000
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19200000
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400000000>;
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};
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qcom,npu-pwrlevel@2 {
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reg = <2>;
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vreg = <3>;
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clk-freq = <19200000
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333000000
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557000000
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557000000
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300000000
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75000000
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533000000
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214000000
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19200000
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50000000
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100000000
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214000000
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214000000
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214000000
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19200000
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214000000
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19200000
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50000000
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557000000
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50000000
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19200000
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557000000
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19200000
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500000000>;
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};
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qcom,npu-pwrlevel@3 {
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reg = <3>;
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vreg = <4>;
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clk-freq = <19200000
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428000000
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729000000
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729000000
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403000000
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75000000
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700000000
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300000000
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19200000
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100000000
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200000000
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300000000
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300000000
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300000000
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19200000
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300000000
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19200000
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100000000
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729000000
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100000000
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19200000
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729000000
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19200000
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660000000>;
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};
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qcom,npu-pwrlevel@4 {
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reg = <4>;
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vreg = <6>;
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clk-freq = <19200000
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500000000
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844000000
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844000000
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533000000
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75000000
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806000000
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300000000
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19200000
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100000000
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200000000
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300000000
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300000000
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300000000
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19200000
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300000000
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19200000
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100000000
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844000000
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100000000
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19200000
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844000000
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19200000
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800000000>;
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};
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qcom,npu-pwrlevel@5 {
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reg = <5>;
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vreg = <7>;
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clk-freq = <19200000
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500000000
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1000000000
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1000000000
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533000000
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75000000
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806000000
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300000000
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19200000
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100000000
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200000000
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300000000
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300000000
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300000000
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19200000
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300000000
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19200000
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100000000
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1000000000
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100000000
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19200000
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1000000000
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19200000
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800000000>;
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};
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};
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};
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};
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