Jilai Wang
83f5fa3cf4
The mailbox controller implemented in NPU works as a bridge between ipcc_mproc mailbox controller and its clients. It is required because npu driver needs to control when IPCC irq can be sent to NPUQ6. Change-Id: I2987c1820169577c6985fa922e2401f865f13b7b
134 lines
3.1 KiB
Devicetree
134 lines
3.1 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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&soc {
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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adsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
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qcom,entry-name = "rdbg";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
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qcom,entry-name = "rdbg";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-dsps {
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compatible = "qcom,smp2p";
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qcom,smem = <481>, <430>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <3>;
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dsps_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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dsps_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sleepstate_smp2p_out: sleepstate-out {
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qcom,entry-name = "sleepstate";
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#qcom,smem-state-cells = <1>;
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};
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sleepstate_smp2p_in: qcom,sleepstate-in {
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qcom,entry-name = "sleepstate_see";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-cdsp {
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compatible = "qcom,smp2p";
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qcom,smem = <94>, <432>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <5>;
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cdsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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cdsp_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out {
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qcom,entry-name = "qvrexternal";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
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qcom,entry-name = "rdbg";
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#qcom,smem-state-cells = <1>;
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};
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smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
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qcom,entry-name = "rdbg";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,smp2p-npu {
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compatible = "qcom,smp2p";
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qcom,smem = <617>, <616>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <10>;
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npu_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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npu_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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