Avaneesh Kumar Dwivedi
446b7b207f
Add initial device tree files to support kona-7230 target. Change-Id: I48979cf561bc75f87547dd1c5b8d49996d61a2df
395 lines
7.1 KiB
Devicetree
395 lines
7.1 KiB
Devicetree
/ {
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/delete-node/ cpus;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_1>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_4>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_5>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU4: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_6>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <514>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU5: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_7>;
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qcom,freq-domain = <&cpufreq_hw 2 4>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <598>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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core2 {
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cpu = <&CPU4>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU5>;
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};
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};
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};
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};
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};
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&soc {
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/delete-node/ dsu_pmu@0;
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/delete-node/ jtagmm@7240000;
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/delete-node/ jtagmm@7340000;
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/delete-node/ cti@7220000;
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/delete-node/ cti@7320000;
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/delete-node/ etm@7240000;
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/delete-node/ etm@7340000;
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dsu_pmu@0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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cpus = <&CPU0>, <&CPU1>,
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<&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
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};
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qcom,lpm-levels {
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qcom,pm-cluster@0 {
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qcom,pm-cpu@0 {
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/delete-property/ qcom,cpu;
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qcom,cpu = <&CPU0 &CPU1>;
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};
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qcom,pm-cpu@1 {
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/delete-property/ qcom,cpu;
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qcom,cpu = <&CPU2 &CPU3 &CPU4 &CPU5>;
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};
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};
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};
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};
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&funnel_apss {
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ports {
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/delete-node/ port@3;
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/delete-node/ port@4;
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};
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};
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&cti_cpu4 {
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/delete-property/ cpu;
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cpu = <&CPU2>;
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};
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&cti_cpu5 {
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/delete-property/ cpu;
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cpu = <&CPU3>;
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};
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&cti_cpu6 {
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/delete-property/ cpu;
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cpu = <&CPU4>;
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};
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&cti_cpu7 {
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/delete-property/ cpu;
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cpu = <&CPU5>;
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};
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&etm4 {
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/delete-property/ cpu;
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cpu = <&CPU2>;
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};
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&etm5 {
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/delete-property/ cpu;
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cpu = <&CPU3>;
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};
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&etm6 {
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/delete-property/ cpu;
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cpu = <&CPU4>;
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};
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&etm7 {
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/delete-property/ cpu;
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cpu = <&CPU5>;
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};
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&jtag_mm4 {
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/delete-property/ qcom,coresight-jtagmm-cpu;
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qcom,coresight-jtagmm-cpu = <&CPU2>;
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};
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&jtag_mm5 {
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/delete-property/ qcom,coresight-jtagmm-cpu;
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qcom,coresight-jtagmm-cpu = <&CPU3>;
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};
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&jtag_mm6 {
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/delete-property/ qcom,coresight-jtagmm-cpu;
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qcom,coresight-jtagmm-cpu = <&CPU4>;
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};
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&jtag_mm7 {
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/delete-property/ qcom,coresight-jtagmm-cpu;
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qcom,coresight-jtagmm-cpu = <&CPU5>;
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};
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&cpu0_memlat_cpugrp {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU0 &CPU1>;
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qcom,cpu0-llcc-ddr-latmon {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU0 &CPU1>;
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};
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};
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&cpu4_memlat_cpugrp {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
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qcom,cpu4-cpu-l3-latmon {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
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};
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qcom,cpu7-cpu-l3-latmon {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU5>;
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};
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qcom,cpu4-llcc-ddr-latmon {
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/delete-property/ qcom,cpulist;
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qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
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};
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};
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&cpufreq_hw {
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/delete-node/ qcom,cpu-isolation;
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qcom,cpu-isolation {
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compatible = "qcom,cpu-isolate";
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cpu0_isolate: cpu0-isolate {
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qcom,cpu = <&CPU0>;
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#cooling-cells = <2>;
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};
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cpu1_isolate: cpu1-isolate {
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qcom,cpu = <&CPU1>;
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#cooling-cells = <2>;
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};
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cpu4_isolate: cpu4-isolate {
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qcom,cpu = <&CPU2>;
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#cooling-cells = <2>;
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};
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cpu5_isolate: cpu5-isolate {
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qcom,cpu = <&CPU3>;
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#cooling-cells = <2>;
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};
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cpu6_isolate: cpu6-isolate {
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qcom,cpu = <&CPU4>;
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#cooling-cells = <2>;
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};
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cpu7_isolate: cpu7-isolate {
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qcom,cpu = <&CPU5>;
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#cooling-cells = <2>;
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};
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};
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/delete-node/ cpu7-notify;
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cpu7_notify: cpu7-notify {
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qcom,cooling-cpu = <&CPU5>;
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#cooling-cells = <2>;
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};
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};
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&thermal_zones {
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/delete-node/ cpu-0-2-step;
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/delete-node/ cpu-0-3-step;
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pop-mem-step {
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cooling-maps {
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pop_cdev4 {
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/delete-property/ cooling-device;
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cooling-device =
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<&CPU2 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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pop_cdev7 {
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/delete-property/ cooling-device;
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cooling-device =
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<&CPU5 THERMAL_NO_LIMIT
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THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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