Naveen Yadav
3cc814eca9
Add flag to avoid GDSC disable when the gdsc is enabled by entity external to HLOS and there is no enable call on the GDSC. Change-Id: I0274d7ed24a0d3cbb5f154a5886ad61d1f111639
149 lines
3.4 KiB
Devicetree
149 lines
3.4 KiB
Devicetree
&soc {
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/* GDSCs in GCC */
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gcc_ufs_phy_gdsc: qcom,gdsc@13a004 {
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compatible = "qcom,gdsc";
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reg = <0x13a004 0x4>;
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regulator-name = "gcc_ufs_phy_gdsc";
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@11a004 {
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compatible = "qcom,gdsc";
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reg = <0x11a004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@1b7040 {
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compatible = "qcom,gdsc";
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reg = <0x1b7040 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@1b7044 {
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compatible = "qcom,gdsc";
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reg = <0x1b7044 0x4>;
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regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in CAMCC */
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cam_cc_bps_gdsc: qcom,gdsc@ad06004 {
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compatible = "qcom,gdsc";
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reg = <0xad06004 0x4>;
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regulator-name = "cam_cc_bps_gdsc";
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status = "disabled";
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};
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cam_cc_ife_0_gdsc: qcom,gdsc@ad09004 {
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compatible = "qcom,gdsc";
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reg = <0xad09004 0x4>;
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regulator-name = "cam_cc_ife_0_gdsc";
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status = "disabled";
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};
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cam_cc_ife_1_gdsc: qcom,gdsc@ad0a004 {
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compatible = "qcom,gdsc";
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reg = <0xad0a004 0x4>;
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regulator-name = "cam_cc_ife_1_gdsc";
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status = "disabled";
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};
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cam_cc_ife_2_gdsc: qcom,gdsc@ad0b004 {
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compatible = "qcom,gdsc";
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reg = <0xad0b004 0x4>;
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regulator-name = "cam_cc_ife_2_gdsc";
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status = "disabled";
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};
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cam_cc_ipe_0_gdsc: qcom,gdsc@ad07004 {
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compatible = "qcom,gdsc";
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reg = <0xad07004 0x4>;
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regulator-name = "cam_cc_ipe_0_gdsc";
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status = "disabled";
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};
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cam_cc_titan_top_gdsc: qcom,gdsc@ad14004 {
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compatible = "qcom,gdsc";
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reg = <0xad14004 0x4>;
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regulator-name = "cam_cc_titan_top_gdsc";
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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mdss_core_gdsc: qcom,gdsc@af01004 {
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compatible = "qcom,gdsc";
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reg = <0xaf01004 0x4>;
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regulator-name = "mdss_core_gdsc";
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qcom,support-hw-trigger;
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_gx_domain_addr: syscon@3d91508 {
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compatible = "syscon";
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reg = <0x3d91508 0x4>;
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};
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gpu_gx_sw_reset: syscon@3d91008 {
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compatible = "syscon";
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reg = <0x3d91008 0x4>;
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};
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gpu_cx_hw_ctrl: syscon@3d91540 {
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compatible = "syscon";
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reg = <0x3d91540 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@3d9106c {
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compatible = "qcom,gdsc";
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reg = <0x3d9106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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qcom,clk-dis-wait-val = <8>;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@3d9100c {
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compatible = "qcom,gdsc";
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reg = <0x3d9100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,skip-disable-before-sw-enable;
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status = "disabled";
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};
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/* GDSCs in NPUCC */
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npu_cc_core_gdsc: qcom,gdsc@9981004 {
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compatible = "qcom,gdsc";
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reg = <0x9981004 0x4>;
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regulator-name = "npu_cc_core_gdsc";
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status = "disabled";
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};
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/* GDSCs in VIDEOCC */
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video_cc_mvs0_gdsc: qcom,gdsc@aaf3004 {
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compatible = "qcom,gdsc";
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reg = <0xaaf3004 0x4>;
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regulator-name = "video_cc_mvs0_gdsc";
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status = "disabled";
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};
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video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {
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compatible = "qcom,gdsc";
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reg = <0xaaf2004 0x4>;
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regulator-name = "video_cc_mvsc_gdsc";
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status = "disabled";
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};
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};
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