Swetha Chikkaboraiah
7babdba8ba
Add initial device tree support for SDM429/439/QM215 target.
This is a snapshot of dtsi files as of msm-4.9
'commit <033db782f19bcc5b961fcb676404466c2c07d0f8>
("msm: kgsl: Protect the memdesc->gpuaddr in SVM use cases")'.
Snapshot of msm-pm8916.dtsi is taken from msm-3.10 And
renamed to pm8916.dtsi to be comaptible with 4.19 kernel
'commit <795bad7cbc25468d9b0dc7c011cc7ef2e3f4c0b2>
power: qpnp-linear-charger: fix mutex lockup")'.
Change-Id: Id25960963b2ffc8bbb23abb6a802d146bb643d02
90 lines
2.7 KiB
Devicetree
90 lines
2.7 KiB
Devicetree
&soc {
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kgsl_smmu: arm,smmu-kgsl@1c40000 {
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status = "ok"
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compatible = "qcom,smmu-v2";
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qcom,tz-device-id = "GPU";
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reg = <0x1c40000 0x10000>;
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#iommu-cells = <1>;
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#global-interrupts = <0>;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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qcom,dynamic;
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qcom,use-3-lvl-tables;
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qcom,enable-smmu-halt;
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qcom,skip-init;
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vdd-supply = <&gdsc_oxili_cx>;
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qcom,regulator-names = "vdd";
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clocks = <&gcc GCC_OXILI_AHB_CLK>,
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<&gcc GCC_BIMC_GFX_CLK>;
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clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
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};
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/* A test device to test the SMMU operation */
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kgsl_iommu_test_device0 {
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status = "disabled";
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compatible = "iommu-debug-test";
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/* The SID should be valid one to get the proper
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*SMR,S2CR indices.
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*/
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iommus = <&kgsl_smmu 0x0>;
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};
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apps_iommu: qcom,iommu@1e00000 {
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status = "okay";
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compatible = "qcom,qsmmu-v500";
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reg = <0x1e00000 0x40000>,
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<0x1ee2000 0x20>;
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reg-names = "base", "tcu-base";
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#iommu-cells = <2>;
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qcom,tz-device-id = "APPS";
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qcom,skip-init;
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qcom,enable-static-cb;
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qcom,use-3-lvl-tables;
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qcom,disable-atos;
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qcom,regulator-names = "vdd";
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#global-interrupts = <0>;
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#size-cells = <1>;
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#address-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_SMMU_CFG_CLK>,
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<&gcc GCC_APSS_TCU_CLK>;
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clock-names = "iface_clk", "core_clk";
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};
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};
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#include "msm-arm-smmu-impl-defs-8937.dtsi"
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