Chandana Kishori Chiluveru
e1f140fe37
Correct the interrupt numbers for GSI node of QUP 1. Change-Id: I8d4a710093bf7e56fdebd903f92f7c56d27ef669
330 lines
9.9 KiB
Devicetree
330 lines
9.9 KiB
Devicetree
#include <dt-bindings/msm/msm-bus-ids.h>
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&soc {
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/* QUPv3 SE Instances
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* North 0 : SE 0
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* North 1 : SE 1
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* North 2 : SE 2
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* South 0 : SE 6
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* South 1 : SE 7
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* South 2 : SE 8
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* South 3 : SE 9
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* South 4 : SE 10
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*/
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/* QUPv3_0 wrapper instance : North QUP */
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qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x8c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
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<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
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iommus = <&apps_smmu 0x43 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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gpi_dma0: qcom,gpi-dma@800000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x800000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <10>;
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qcom,gpii-mask = <0x1f>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x56 0x0>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "ok"
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};
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qupv3_se0_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 0 3 64 0>,
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<&gpi_dma0 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_i2c_active>;
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pinctrl-1 = <&qupv3_se0_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se0_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x880000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se0_spi_active>;
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pinctrl-1 = <&qupv3_se0_spi_sleep>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 0 1 64 0>,
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<&gpi_dma0 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se1_4uart: qcom,qup_uart@884000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x884000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "active", "sleep";
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pinctrl-0 = <&qupv3_se1_default_ctsrtsrx>,
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<&qupv3_se1_default_tx>;
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pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
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<&qupv3_se1_tx>;
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pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
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<&qupv3_se1_tx>;
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interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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qupv3_se2_i2c: i2c@888000 {
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compatible = "qcom,i2c-geni";
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reg = <0x888000 0x4000>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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dmas = <&gpi_dma0 0 2 3 64 0>,
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<&gpi_dma0 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_i2c_active>;
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pinctrl-1 = <&qupv3_se2_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_0>;
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status = "disabled";
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};
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qupv3_se2_spi: spi@888000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x888000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se2_spi_active>;
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pinctrl-1 = <&qupv3_se2_spi_sleep>;
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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dmas = <&gpi_dma0 0 2 1 64 0>,
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<&gpi_dma0 1 2 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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/* QUPv3_1 wrapper instance : South QUP */
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qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-bus-ids =
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<MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
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<MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
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iommus = <&apps_smmu 0x4c3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-dma = "fastmap";
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};
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gpi_dma1: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <10>;
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qcom,gpii-mask = <0x3f>;
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qcom,ev-factor = <2>;
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iommus = <&apps_smmu 0x4d6 0x0>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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status = "ok"
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};
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qupv3_se6_i2c: i2c@980000 {
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compatible = "qcom,i2c-geni";
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reg = <0x980000 0x4000>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 0 3 64 0>,
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<&gpi_dma1 1 0 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_i2c_active>;
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pinctrl-1 = <&qupv3_se6_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se6_spi: spi@980000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x980000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_spi_active>;
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pinctrl-1 = <&qupv3_se6_spi_sleep>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_1>;
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dmas = <&gpi_dma1 0 0 1 64 0>,
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<&gpi_dma1 1 0 1 64 0>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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qupv3_se7_2uart: qcom,qup_uart@984000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x984000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_2uart_active>;
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pinctrl-1 = <&qupv3_se7_2uart_sleep>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se7_i2c: i2c@984000 {
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compatible = "qcom,i2c-geni";
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reg = <0x984000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 1 3 64 0>,
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<&gpi_dma1 1 1 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se7_i2c_active>;
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pinctrl-1 = <&qupv3_se7_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se8_i2c: i2c@988000 {
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compatible = "qcom,i2c-geni";
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reg = <0x988000 0x4000>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 2 3 64 0>,
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<&gpi_dma1 1 2 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se8_i2c_active>;
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pinctrl-1 = <&qupv3_se8_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "disabled";
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};
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qupv3_se9_2uart: qcom,qup_uart@98c000 {
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compatible = "qcom,msm-geni-console";
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reg = <0x98c000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se9_2uart_active>;
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pinctrl-1 = <&qupv3_se9_2uart_sleep>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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qcom,wrapper-core = <&qupv3_1>;
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status = "ok"
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};
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qupv3_se10_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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dmas = <&gpi_dma1 0 4 3 64 0>,
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<&gpi_dma1 1 4 3 64 0>;
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dma-names = "tx", "rx";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se10_i2c_active>;
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pinctrl-1 = <&qupv3_se10_i2c_sleep>;
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qcom,wrapper-core = <&qupv3_1>;
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qcom,shared;
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status = "disabled";
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};
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};
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