Priyanka Gujjula
b95cc6b4e5
Update correct low SVS corner from (133.33) to (133.25) for core clock and vcodec clock. Change-Id: I4e2e8498b1e2e20a33d12f4b1c20c067badff837
222 lines
6.3 KiB
Devicetree
222 lines
6.3 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/msm/msm-bus-ids.h>
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#include <dt-bindings/clock/qcom,videocc-lagoon.h>
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&soc {
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msm_vidc0: qcom,vidc0 {
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compatible = "qcom,msm-vidc", "qcom,lagoon-vidc";
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status = "ok"
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sku-index = <0>;
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reg = <0xaa00000 0x0100000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* Supply */
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iris-ctl-supply = <&video_cc_mvsc_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "video_cc_mvsc_ctl_axi",
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"video_cc_mvs0_ctl_axi", "core_clk",
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"vcodec_clk", "iface_clk";
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clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
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<&videocc VIDEO_CC_MVS0_AXI_CLK>,
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<&videocc VIDEO_CC_MVSC_CORE_CLK>,
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<&videocc VIDEO_CC_MVS0_CORE_CLK>,
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<&videocc VIDEO_CC_VENUS_AHB_CLK>;
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qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
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"video_cc_mvs0_ctl_axi", "core_clk",
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"vcodec_clk", "iface_clk";
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qcom,clock-configs = <0x0 0x0 0x1 0x1 0x0>;
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qcom,allowed-clock-rates = <133250000 240000000
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300000000 380000000 460000000>;
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qcom,reg-presets = <0xB0084 0x0>,
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<0xB0088 0x0>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-vidc,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,mode = "performance";
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qcom,bus-range-kbps = <762 762>;
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};
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venus_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,mode = "venus-ddr";
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qcom,bus-range-kbps = <762 15000000>;
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};
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arm9_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-arm9-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,mode = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&apps_smmu 0xc00 0x20>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x25800000 0xba800000>;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&apps_smmu 0xc04 0x20>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
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buffer-types = <0x480>;
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virtual-addr-pool = <0x1000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&apps_smmu 0xc01 0x04>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
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buffer-types = <0x241>;
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virtual-addr-pool = <0x500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&apps_smmu 0xc03 0x00>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
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buffer-types = <0x106>;
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virtual-addr-pool = <0x500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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};
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msm_vidc1: qcom,vidc1 {
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compatible = "qcom,msm-vidc", "qcom,lagoon-vidc";
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status = "ok"
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sku-index = <1>;
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reg = <0xaa00000 0x0100000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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/* Supply */
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iris-ctl-supply = <&video_cc_mvsc_gdsc>;
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vcodec-supply = <&video_cc_mvs0_gdsc>;
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/* Clocks */
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clock-names = "video_cc_mvsc_ctl_axi",
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"video_cc_mvs0_ctl_axi", "core_clk",
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"vcodec_clk", "iface_clk";
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clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
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<&videocc VIDEO_CC_MVS0_AXI_CLK>,
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<&videocc VIDEO_CC_MVSC_CORE_CLK>,
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<&videocc VIDEO_CC_MVS0_CORE_CLK>,
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<&videocc VIDEO_CC_VENUS_AHB_CLK>;
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qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
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"video_cc_mvs0_ctl_axi", "core_clk",
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"vcodec_clk", "iface_clk";
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qcom,clock-configs = <0x0 0x0 0x1 0x1 0x0>;
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qcom,allowed-clock-rates = <133250000 240000000
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300000000 380000000>;
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qcom,reg-presets = <0xB0084 0x0>,
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<0xB0088 0x0>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-vidc,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,mode = "performance";
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qcom,bus-range-kbps = <762 762>;
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};
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venus_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,mode = "venus-ddr";
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qcom,bus-range-kbps = <762 15000000>;
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};
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arm9_bus_ddr {
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compatible = "qcom,msm-vidc,bus";
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label = "venus-arm9-ddr";
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qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
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qcom,mode = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_ns";
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iommus = <&apps_smmu 0xc00 0x20>;
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qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
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qcom,iommu-faults = "non-fatal";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x25800000 0xba800000>;
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};
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secure_non_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_non_pixel";
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iommus = <&apps_smmu 0xc04 0x20>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
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buffer-types = <0x480>;
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virtual-addr-pool = <0x1000000 0x24800000>;
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qcom,secure-context-bank;
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};
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secure_bitstream_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_bitstream";
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iommus = <&apps_smmu 0xc01 0x04>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
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buffer-types = <0x241>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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secure_pixel_cb {
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compatible = "qcom,msm-vidc,context-bank";
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label = "venus_sec_pixel";
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iommus = <&apps_smmu 0xc03 0x00>;
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qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
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buffer-types = <0x106>;
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virtual-addr-pool = <0x00500000 0xdfb00000>;
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qcom,secure-context-bank;
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};
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};
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};
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