Naveen Yadav
b274b65dea
Add debug clock controller node to use the debug clock controller driver for measuring the clocks. Also add MCCC and CPUCC device and phandle reference to debugcc to map register space for the apss specific debug mux. Also, Update the GPUCC node to use the real clock controller and also update the GDSCs for GPUCC. Change-Id: Ic5c90bda2f34c30ae9ce716cfae39ef98bec50c6
112 lines
2.6 KiB
Devicetree
112 lines
2.6 KiB
Devicetree
&soc {
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/* GDSCs in GCC */
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gcc_camss_top_gdsc: qcom,gdsc@1458004 {
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compatible = "qcom,gdsc";
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reg = <0x1458004 0x4>;
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regulator-name = "gcc_camss_top_gdsc";
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status = "disabled";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
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compatible = "qcom,gdsc";
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reg = <0x141a004 0x4>;
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regulator-name = "gcc_usb30_prim_gdsc";
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status = "disabled";
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};
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gcc_vcodec0_gdsc: qcom,gdsc@1458098 {
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compatible = "qcom,gdsc";
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reg = <0x1458098 0x4>;
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regulator-name = "gcc_vcodec0_gdsc";
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status = "disabled";
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};
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gcc_venus_gdsc: qcom,gdsc@145807c {
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compatible = "qcom,gdsc";
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reg = <0x145807c 0x4>;
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regulator-name = "gcc_venus_gdsc";
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
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compatible = "qcom,gdsc";
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reg = <0x147d074 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
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compatible = "qcom,gdsc";
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reg = <0x147d078 0x4>;
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regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
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compatible = "qcom,gdsc";
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reg = <0x147d060 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
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compatible = "qcom,gdsc";
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reg = <0x147d07c 0x4>;
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regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
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qcom,no-status-check-on-disable;
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qcom,gds-timeout = <500>;
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status = "disabled";
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};
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/* GDSCs in DISPCC */
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mdss_core_gdsc: qcom,gdsc@5f03000 {
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compatible = "qcom,gdsc";
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reg = <0x5f03000 0x4>;
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regulator-name = "mdss_core_gdsc";
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proxy-supply = <&mdss_core_gdsc>;
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qcom,proxy-consumer-enable;
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status = "disabled";
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};
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/* GDSCs in GPUCC */
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gpu_cx_hw_ctrl: syscon@5991540 {
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compatible = "syscon";
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reg = <0x5991540 0x4>;
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};
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gpu_gx_sw_reset: syscon@5991008 {
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compatible = "syscon";
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reg = <0x5991008 0x4>;
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};
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gpu_gx_domain_addr: syscon@5991508 {
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compatible = "syscon";
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reg = <0x5991508 0x4>;
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};
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gpu_cx_gdsc: qcom,gdsc@599106c {
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compatible = "qcom,gdsc";
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reg = <0x599106c 0x4>;
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regulator-name = "gpu_cx_gdsc";
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hw-ctl-addr = <&gpu_cx_hw_ctrl>;
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qcom,no-status-check-on-disable;
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status = "disabled";
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};
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gpu_gx_gdsc: qcom,gdsc@599100c {
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compatible = "qcom,gdsc";
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reg = <0x599100c 0x4>;
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regulator-name = "gpu_gx_gdsc";
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sw-reset = <&gpu_gx_sw_reset>;
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domain-addr = <&gpu_gx_domain_addr>;
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qcom,reset-aon-logic;
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status = "disabled";
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};
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};
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