Indira Biruduraju
20ac6d8217
Update bandwidth voting for NOM and NOM_L1 GPU corners to save power in some of the gaming usecases. Change-Id: I9f0f329ba8d8b70cefa27745e71a2671f4a637c5
631 lines
14 KiB
Devicetree
631 lines
14 KiB
Devicetree
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
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&soc {
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pil_gpu: qcom,kgsl-hyp {
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compatible = "qcom,pil-tz-generic";
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qcom,pas-id = <13>;
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qcom,firmware-name = "a615_zap";
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};
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msm_bus: qcom,kgsl-busmon {
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label = "kgsl-busmon";
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compatible = "qcom,kgsl-busmon";
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operating-points-v2 = <&gpu_opp_table>;
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};
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gpubw: qcom,gpubw {
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compatible = "qcom,devbw";
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governor = "bw_vbif";
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qcom,src-dst-ports = <26 512>;
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operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-850000000 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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opp-565000000 {
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opp-hz = /bits/ 64 <565000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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opp-430000000 {
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opp-hz = /bits/ 64 <430000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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opp-355000000 {
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opp-hz = /bits/ 64 <355000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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opp-253000000 {
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opp-hz = /bits/ 64 <253000000>;
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opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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msm_gpu: qcom,kgsl-3d0@3d00000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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status = "ok"
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reg = <0x3d00000 0x40000>,
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<0x3d61000 0x800>,
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<0x3d9e000 0x1000>;
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reg-names = "kgsl_3d0_reg_memory",
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"cx_dbgc", "cx_misc";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x06010900>;
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qcom,gpu-quirk-hfi-use-reg;
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qcom,gpu-quirk-secvid-set-once;
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/* <HZ/12> */
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qcom,idle-timeout = <80>;
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qcom,no-nap;
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qcom,highest-bank-bit = <14>;
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qcom,min-access-length = <32>;
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qcom,ubwc-mode = <2>;
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/* size in bytes */
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qcom,snapshot-size = <0x200000>;
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clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gpucc GPU_CC_CX_GMU_CLK>;
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clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
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"mem_iface_clk", "gmu_clk";
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/* QDSS_STM base addr, size */
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qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
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#cooling-cells = <2>;
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qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
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/* Bus Scale Settings */
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qcom,gpubw-dev = <&gpubw>;
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qcom,bus-control;
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qcom,msm-bus,name = "grp3d";
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qcom,msm-bus,num-cases = <13>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>,
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<26 512 0 400000>, /* 1 bus=100 */
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<26 512 0 800000>, /* 2 bus=200 */
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<26 512 0 1200000>, /* 3 bus=300 */
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<26 512 0 1804800>, /* 4 bus=451 */
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<26 512 0 2188000>, /* 5 bus=547 */
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<26 512 0 2724000>, /* 6 bus=681 */
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<26 512 0 3072000>, /* 7 bus=768 */
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<26 512 0 4068000>, /* 8 bus=1017 */
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<26 512 0 5412000>, /* 9 bus=1353 */
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<26 512 0 6220000>, /* 10 bus=1555 */
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<26 512 0 7216000>, /* 11 bus=1804 */
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<26 512 0 8371200>; /* 12 bus=2092 */
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/* GDSC regulator names */
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regulator-names = "vddcx", "vdd";
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/* GDSC oxili regulators */
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vddcx-supply = <&gpu_cx_gdsc>;
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vdd-supply = <&gpu_gx_gdsc>;
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nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
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nvmem-cell-names = "speed_bin", "gaming_bin";
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/* CPU latency parameter */
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qcom,pm-qos-active-latency = <67>;
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qcom,pm-qos-wakeup-latency = <67>;
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/* Enable context aware freq. scaling */
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qcom,enable-ca-jump;
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/* Context aware jump busy penalty in us */
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qcom,ca-busy-penalty = <12000>;
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/* GPU OPP data */
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operating-points-v2 = <&gpu_opp_table>;
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/* GPU Mempools */
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qcom,gpu-mempools {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-mempools";
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/* 4K Page Pool configuration */
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qcom,gpu-mempool@0 {
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reg = <0>;
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qcom,mempool-page-size = <4096>;
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qcom,mempool-allocate;
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};
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/* 8K Page Pool configuration */
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qcom,gpu-mempool@1 {
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reg = <1>;
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qcom,mempool-page-size = <8192>;
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qcom,mempool-allocate;
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};
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/* 64K Page Pool configuration */
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qcom,gpu-mempool@2 {
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reg = <2>;
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qcom,mempool-page-size = <65536>;
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qcom,mempool-reserved = <256>;
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};
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/* 1M Page Pool configuration */
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qcom,gpu-mempool@3 {
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reg = <3>;
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qcom,mempool-page-size = <1048576>;
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qcom,mempool-reserved = <32>;
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};
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};
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/*
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* Speed-bin zero is default speed bin.
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* For rest of the speed bins, speed-bin value
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* is calulated as FMAX/4.8 MHz (round up to zero
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* decimal places) + 2.
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*/
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible="qcom,gpu-pwrlevel-bins";
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <0>;
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qcom,ca-target-pwrlevel = <5>;
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qcom,initial-pwrlevel = <6>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <850000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <800000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <650000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <565000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <430000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <355000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <253000000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <180>;
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qcom,ca-target-pwrlevel = <5>;
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qcom,initial-pwrlevel = <6>;
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/* TURBO_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <850000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* TURBO */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <800000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <650000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <565000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <430000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <355000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <253000000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <169>;
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qcom,ca-target-pwrlevel = <4>;
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qcom,initial-pwrlevel = <5>;
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/* TURBO */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <800000000>;
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qcom,bus-freq = <12>;
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qcom,bus-min = <10>;
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qcom,bus-max = <12>;
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};
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/* NOM_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <650000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <565000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <10>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <430000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <355000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <253000000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-3 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <120>;
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qcom,ca-target-pwrlevel = <2>;
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qcom,initial-pwrlevel = <3>;
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/* NOM */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <565000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <430000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <355000000>;
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qcom,bus-freq = <7>;
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qcom,bus-min = <5>;
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qcom,bus-max = <8>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <253000000>;
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qcom,bus-freq = <5>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* LOW SVS */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <0>;
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qcom,bus-freq = <0>;
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qcom,bus-min = <0>;
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qcom,bus-max = <0>;
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};
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};
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qcom,gpu-pwrlevels-4 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,speed-bin = <138>;
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qcom,ca-target-pwrlevel = <3>;
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qcom,initial-pwrlevel = <4>;
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/* NOM_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <650000000>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <8>;
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qcom,bus-max = <12>;
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};
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/* NOM */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <565000000>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <8>;
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qcom,bus-max = <11>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <430000000>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <10>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
|
|
qcom,gpu-freq = <355000000>;
|
|
qcom,bus-freq = <7>;
|
|
qcom,bus-min = <5>;
|
|
qcom,bus-max = <8>;
|
|
};
|
|
|
|
/* LOW SVS */
|
|
qcom,gpu-pwrlevel@4 {
|
|
reg = <4>;
|
|
qcom,gpu-freq = <253000000>;
|
|
qcom,bus-freq = <5>;
|
|
qcom,bus-min = <4>;
|
|
qcom,bus-max = <7>;
|
|
};
|
|
|
|
/* LOW SVS */
|
|
qcom,gpu-pwrlevel@5 {
|
|
reg = <5>;
|
|
qcom,gpu-freq = <0>;
|
|
qcom,bus-freq = <0>;
|
|
qcom,bus-min = <0>;
|
|
qcom,bus-max = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,cpu-to-gpu-cfg-path {
|
|
qcom,msm-bus,name = "gpu_cfg";
|
|
qcom,msm-bus,num-cases = <3>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 598 0 0>, // off
|
|
<1 598 0 100>, // min freq
|
|
<1 598 0 9999999>; // max freq
|
|
};
|
|
};
|
|
|
|
kgsl_msm_iommu: qcom,kgsl-iommu@3d40000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
reg = <0x3d40000 0x10000>;
|
|
qcom,protect = <0x40000 0x10000>;
|
|
qcom,micro-mmu-control = <0x6000>;
|
|
|
|
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
|
|
|
clock-names = "iface_clk", "mem_clk", "mem_iface_clk";
|
|
|
|
qcom,secure_align_mask = <0xfff>;
|
|
qcom,retention;
|
|
qcom,hyp_secure_alloc;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
label = "gfx3d_user";
|
|
iommus = <&kgsl_smmu 0>;
|
|
qcom,iommu-dma = "disabled";
|
|
qcom,gpu-offset = <0x48000>;
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <&kgsl_smmu 2>;
|
|
};
|
|
};
|
|
|
|
gmu: qcom,gmu@3d6a000 {
|
|
label = "kgsl-gmu";
|
|
compatible = "qcom,gpu-gmu";
|
|
|
|
reg = <0x3d6a000 0x31000>,
|
|
<0xb290000 0x10000>,
|
|
<0xb490000 0x10000>;
|
|
reg-names = "kgsl_gmu_reg",
|
|
"kgsl_gmu_pdc_cfg",
|
|
"kgsl_gmu_pdc_seq";
|
|
|
|
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
|
|
|
|
qcom,msm-bus,name = "cnoc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<26 10036 0 0>, /* CNOC off */
|
|
<26 10036 0 100>; /* CNOC on */
|
|
|
|
regulator-names = "vddcx", "vdd";
|
|
vddcx-supply = <&gpu_cx_gdsc>;
|
|
vdd-supply = <&gpu_gx_gdsc>;
|
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
|
|
|
|
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
|
"memnoc_clk";
|
|
|
|
gmu_user: gmu_user {
|
|
compatible = "qcom,smmu-gmu-user-cb";
|
|
iommus = <&kgsl_smmu 4>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
|
|
gmu_kernel: gmu_kernel {
|
|
compatible = "qcom,smmu-gmu-kernel-cb";
|
|
iommus = <&kgsl_smmu 5>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|
|
};
|