Satya Rama Aditya Pinapala
e417e43eb5
No separate supplies are required for enabling DSI PLL as it is enabled with GDSC which is hardware controlled. This change removes the unnecessary supply entry node on Kona target. CRs-Fixed: 2573963 Change-Id: I2ff3347520341467de263c520fbe43d63dcc7866
68 lines
1.8 KiB
Devicetree
68 lines
1.8 KiB
Devicetree
&soc {
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mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {
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compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0xae94900 0x260>,
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<0xae94400 0x800>,
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<0xaf03000 0x8>,
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<0xae94200 0x100>;
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reg-names = "pll_base", "phy_base", "gdsc_base",
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"dynamic_pll_base";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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memory-region = <&dfps_data_memory>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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};
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mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {
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compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
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label = "MDSS DSI 1 PLL";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0xae96900 0x260>,
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<0xae96400 0x800>,
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<0xaf03000 0x8>,
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<0xae96200 0x100>;
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reg-names = "pll_base", "phy_base", "gdsc_base",
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"dynamic_pll_base";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
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clock-names = "iface_clk";
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clock-rate = <0>;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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};
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mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
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compatible = "qcom,mdss_dp_pll_7nm";
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label = "MDSS DP PLL";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0x088ea000 0x200>,
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<0x088eaa00 0x200>,
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<0x088ea200 0x200>,
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<0x088ea2b8 0x8>,
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<0x088ea2e8 0x4>,
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<0x088ea600 0x200>,
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<0x088ea6b8 0x8>,
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<0x088ea6e8 0x4>,
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<0xaf03000 0x8>;
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reg-names = "pll_base", "phy_base",
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"ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
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"ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
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"gdsc_base";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_DISP_AHB_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "iface_clk", "ref_clk_src",
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"gcc_iface", "pipe_clk";
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clock-rate = <0>;
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};
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};
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