Soumya Managoli
8d6d1f0d67
Update swr version to 1.5.1 for lito, kona and lagoon. Change-Id: Ibeb3c6a870a08893967bda17fe4bd7fb33676d7b
547 lines
17 KiB
Devicetree
547 lines
17 KiB
Devicetree
#include <dt-bindings/clock/qcom,audio-ext-clk.h>
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#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
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#include <dt-bindings/sound/audio-codec-port-types.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "lagoon-lpi.dtsi"
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&bolero {
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qcom,num-macros = <4>;
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bolero-clk-rsc-mngr {
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compatible = "qcom,bolero-clk-rsc-mngr";
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qcom,fs-gen-sequence = <0x3000 0x1>,
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<0x3004 0x1>, <0x3080 0x2>;
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qcom,rx_mclk_mode_muxsel = <0x033240D8>;
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qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
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qcom,va_mclk_mode_muxsel = <0x033A0000>;
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clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
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"wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
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clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
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<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
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<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
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<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
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};
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tx_macro: tx-macro@3220000 {
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compatible = "qcom,tx-macro";
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reg = <0x3220000 0x0>;
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clock-names = "tx_core_clk", "tx_npl_clk";
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clocks = <&clock_audio_tx_1 0>,
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<&clock_audio_tx_2 0>;
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qcom,tx-swr-gpios = <&tx_swr_gpios>;
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qcom,tx-dmic-sample-rate = <2400000>;
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swr2: tx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr-master-version = <0x01050001>;
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qcom,swr_master_id = <3>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x3230000 0x0>;
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interrupts-extended =
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<&intc GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 144 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq", "swr_wake_irq";
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qcom,swr-wakeup-required = <1>;
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qcom,swr-num-ports = <5>;
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qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
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<2 ADC1 0x1>, <2 ADC2 0x2>,
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<3 ADC3 0x1>, <3 ADC4 0x2>,
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<4 DMIC0 0x1>, <4 DMIC1 0x2>,
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<4 DMIC2 0x4>, <4 DMIC3 0x8>,
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<5 DMIC4 0x1>, <5 DMIC5 0x2>,
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<5 DMIC6 0x4>, <5 DMIC7 0x8>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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qcom,swr-mstr-irq-wakeup-capable = <1>;
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wcd938x_tx_slave: wcd938x-tx-slave {
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compatible = "qcom,wcd938x-slave";
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reg = <0x0D 0x01170223>;
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};
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wcd937x_tx_slave: wcd937x-tx-slave {
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status = "disabled";
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compatible = "qcom,wcd937x-slave";
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reg = <0x0A 0x01170223>;
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};
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};
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};
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rx_macro: rx-macro@3200000 {
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compatible = "qcom,rx-macro";
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reg = <0x3200000 0x0>;
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clock-names = "rx_core_clk", "rx_npl_clk";
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clocks = <&clock_audio_rx_1 0>,
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<&clock_audio_rx_2 0>;
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qcom,rx-swr-gpios = <&rx_swr_gpios>;
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qcom,rx_mclk_mode_muxsel = <0x033240D8>;
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qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x02 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr1: rx_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr-master-version = <0x01050001>;
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qcom,swr_master_id = <2>;
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qcom,mipi-sdw-block-packing-mode = <1>;
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swrm-io-base = <0x3210000 0x0>;
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interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <5>;
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qcom,disable-div2-clk-switch = <1>;
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qcom,swr-port-mapping = <1 HPH_L 0x1>,
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<1 HPH_R 0x2>, <2 CLSH 0x1>,
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<3 COMP_L 0x1>, <3 COMP_R 0x2>,
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<4 LO 0x1>, <5 DSD_L 0x1>,
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<5 DSD_R 0x2>;
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qcom,swr-num-dev = <1>;
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qcom,swr-clock-stop-mode0 = <1>;
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wcd938x_rx_slave: wcd938x-rx-slave {
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compatible = "qcom,wcd938x-slave";
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reg = <0x0D 0x01170224>;
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};
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wcd937x_rx_slave: wcd937x_rx_slave {
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status = "disabled";
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compatible = "qcom,wcd937x-slave";
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reg = <0x0A 0x01170224>;
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};
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};
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};
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wsa_macro: wsa-macro@3240000 {
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compatible = "qcom,wsa-macro";
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reg = <0x3240000 0x0>;
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clock-names = "wsa_core_clk", "wsa_npl_clk";
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clocks = <&clock_audio_wsa_1 0>,
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<&clock_audio_wsa_2 0>;
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qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
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qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x02 0x1E>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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swr0: wsa_swr_master {
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compatible = "qcom,swr-mstr";
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#address-cells = <2>;
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#size-cells = <0>;
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clock-names = "lpass_core_hw_vote",
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"lpass_audio_hw_vote";
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clocks = <&lpass_core_hw_vote 0>,
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<&lpass_audio_hw_vote 0>;
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qcom,swr-master-version = <0x01050001>;
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qcom,swr_master_id = <1>;
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qcom,mipi-sdw-block-packing-mode = <0>;
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swrm-io-base = <0x3250000 0x0>;
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interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "swr_master_irq";
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qcom,swr-num-ports = <8>;
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qcom,swr-port-mapping = <1 SPKR_L 0x1>,
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<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
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<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
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<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
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<8 SPKR_R_VI 0x3>;
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qcom,swr-num-dev = <2>;
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wsa883x_0221: wsa883x@02170221 {
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compatible = "qcom,wsa883x";
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reg = <0x02 0x02170221>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
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qcom,bolero-handle = <&bolero>;
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cdc-vdd-1p8-supply = <&L11A>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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};
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wsa883x_0222: wsa883x@02170222 {
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compatible = "qcom,wsa883x";
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reg = <0x02 0x02170222>;
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qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
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qcom,bolero-handle = <&bolero>;
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cdc-vdd-1p8-supply = <&L11A>;
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qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
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qcom,cdc-vdd-1p8-current = <20000>;
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qcom,cdc-vdd-1p8-lpm-supported = <1>;
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qcom,cdc-static-supplies = "cdc-vdd-1p8";
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};
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};
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};
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va_macro: va-macro@3370000 {
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compatible = "qcom,va-macro";
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reg = <0x3370000 0x0>;
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clock-names = "lpass_audio_hw_vote";
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clocks = <&lpass_audio_hw_vote 0>;
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qcom,va-dmic-sample-rate = <600000>;
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qcom,va-clk-mux-select = <1>;
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qcom,va-island-mode-muxsel = <0x033A0000>;
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qcom,default-clk-id = <TX_CORE_CLK>;
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};
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wcd938x_codec: wcd938x-codec {
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compatible = "qcom,wcd938x-codec";
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qcom,split-codec = <1>;
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
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<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
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<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
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<4 DSD_R 0x2 0 DSD_R>;
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qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
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<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
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<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
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<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
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<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
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<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
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<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
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qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
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qcom,rx-slave = <&wcd938x_rx_slave>;
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qcom,tx-slave = <&wcd938x_tx_slave>;
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cdc-vdd-rxtx-supply = <&L11A>;
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qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
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qcom,cdc-vdd-rxtx-current = <30000>;
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qcom,cdc-vdd-rxtx-lpm-supported = <1>;
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cdc-vddio-supply = <&L11A>;
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qcom,cdc-vddio-voltage = <1800000 1800000>;
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qcom,cdc-vddio-current = <30000>;
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qcom,cdc-vddio-lpm-supported = <1>;
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cdc-vdd-buck-supply = <&L14A>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-vdd-mic-bias-supply = <&BOB>;
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qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
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qcom,cdc-vdd-mic-bias-current = <30000>;
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qcom,cdc-micbias1-mv = <1800>;
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qcom,cdc-micbias2-mv = <1800>;
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qcom,cdc-micbias3-mv = <1800>;
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qcom,cdc-micbias4-mv = <1800>;
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qcom,cdc-static-supplies = "cdc-vdd-rxtx",
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"cdc-vddio",
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"cdc-vdd-mic-bias";
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qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
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};
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wcd937x_codec: wcd937x-codec {
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status = "disabled";
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compatible = "qcom,wcd937x-codec";
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qcom,split-codec = <1>;
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qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
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<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
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<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
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<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
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<4 DSD_R 0x2 0 DSD_R>;
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qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
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<1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
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<2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
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<2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
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<3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
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<3 DMIC5 0x8 0 DMIC7>;
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qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
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qcom,rx-slave = <&wcd937x_rx_slave>;
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qcom,tx-slave = <&wcd937x_tx_slave>;
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cdc-vdd-rxtx-supply = <&L11A>;
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qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
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qcom,cdc-vdd-rxtx-current = <30000>;
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cdc-vddio-supply = <&L11A>;
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qcom,cdc-vddio-voltage = <1800000 1800000>;
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qcom,cdc-vddio-current = <30000>;
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cdc-vdd-buck-supply = <&L14A>;
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qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
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qcom,cdc-vdd-buck-current = <650000>;
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cdc-vdd-mic-bias-supply = <&BOB>;
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qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
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qcom,cdc-vdd-mic-bias-current = <30000>;
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qcom,cdc-micbias1-mv = <1800>;
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qcom,cdc-micbias2-mv = <1800>;
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qcom,cdc-micbias3-mv = <1800>;
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qcom,cdc-micbias4-mv = <1800>;
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qcom,cdc-static-supplies = "cdc-vdd-rxtx",
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"cdc-vddio",
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"cdc-vdd-mic-bias";
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qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
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};
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};
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&lagoon_snd {
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qcom,model = "lito-lagoonmtp-snd-card";
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qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
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qcom,wcn-btfm = <1>;
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qcom,ext-disp-audio-rx = <1>;
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qcom,audio-routing =
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"AMIC1", "MIC BIAS1",
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"MIC BIAS1", "Analog Mic1",
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"AMIC2", "MIC BIAS2",
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"MIC BIAS2", "Analog Mic2",
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"AMIC3", "MIC BIAS3",
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"MIC BIAS3", "Analog Mic3",
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"AMIC4", "MIC BIAS3",
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"MIC BIAS3", "Analog Mic4",
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"AMIC5", "MIC BIAS4",
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"MIC BIAS4", "Analog Mic5",
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"TX DMIC0", "MIC BIAS1",
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"MIC BIAS1", "Digital Mic0",
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"TX DMIC1", "MIC BIAS1",
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"MIC BIAS1", "Digital Mic1",
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"TX DMIC2", "MIC BIAS3",
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"MIC BIAS3", "Digital Mic2",
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"TX DMIC3", "MIC BIAS3",
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"MIC BIAS3", "Digital Mic3",
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"TX DMIC4", "MIC BIAS4",
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"MIC BIAS4", "Digital Mic4",
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"TX DMIC5", "MIC BIAS4",
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"MIC BIAS4", "Digital Mic5",
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"IN1_HPHL", "HPHL_OUT",
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"IN2_HPHR", "HPHR_OUT",
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"IN3_AUX", "AUX_OUT",
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"TX SWR_ADC0", "ADC1_OUTPUT",
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"TX SWR_ADC1", "ADC2_OUTPUT",
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"TX SWR_ADC2", "ADC3_OUTPUT",
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"TX SWR_ADC3", "ADC4_OUTPUT",
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"TX SWR_DMIC0", "DMIC1_OUTPUT",
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"TX SWR_DMIC1", "DMIC2_OUTPUT",
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"TX SWR_DMIC2", "DMIC3_OUTPUT",
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"TX SWR_DMIC3", "DMIC4_OUTPUT",
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"TX SWR_DMIC4", "DMIC5_OUTPUT",
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"TX SWR_DMIC5", "DMIC6_OUTPUT",
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"TX SWR_DMIC6", "DMIC7_OUTPUT",
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"TX SWR_DMIC7", "DMIC8_OUTPUT",
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"WSA SRC0_INP", "SRC0",
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"WSA_TX DEC0_INP", "TX DEC0 MUX",
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"WSA_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC0_INP", "TX DEC0 MUX",
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"RX_TX DEC1_INP", "TX DEC1 MUX",
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"RX_TX DEC2_INP", "TX DEC2 MUX",
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"RX_TX DEC3_INP", "TX DEC3 MUX",
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"SpkrLeft IN", "WSA_SPK1 OUT",
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"SpkrRight IN", "WSA_SPK2 OUT",
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"VA_AIF1 CAP", "VA_SWR_CLK",
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"VA_AIF2 CAP", "VA_SWR_CLK",
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"VA_AIF3 CAP", "VA_SWR_CLK",
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"VA MIC BIAS1", "Digital Mic0",
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"VA MIC BIAS1", "Digital Mic1",
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"VA MIC BIAS3", "Digital Mic2",
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"VA MIC BIAS3", "Digital Mic3",
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"VA MIC BIAS4", "Digital Mic4",
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"VA MIC BIAS4", "Digital Mic5",
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"VA DMIC0", "VA MIC BIAS1",
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"VA DMIC1", "VA MIC BIAS1",
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"VA DMIC2", "VA MIC BIAS3",
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"VA DMIC3", "VA MIC BIAS3",
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"VA DMIC4", "VA MIC BIAS4",
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"VA DMIC5", "VA MIC BIAS4",
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"VA SWR_ADC0", "VA_SWR_CLK",
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"VA SWR_ADC1", "VA_SWR_CLK",
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"VA SWR_ADC2", "VA_SWR_CLK",
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"VA SWR_ADC3", "VA_SWR_CLK",
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"VA SWR_MIC0", "VA_SWR_CLK",
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"VA SWR_MIC1", "VA_SWR_CLK",
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"VA SWR_MIC2", "VA_SWR_CLK",
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"VA SWR_MIC3", "VA_SWR_CLK",
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"VA SWR_MIC4", "VA_SWR_CLK",
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"VA SWR_MIC5", "VA_SWR_CLK",
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"VA SWR_MIC6", "VA_SWR_CLK",
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"VA SWR_MIC7", "VA_SWR_CLK",
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"VA SWR_ADC0", "ADC1_OUTPUT",
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"VA SWR_ADC1", "ADC2_OUTPUT",
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"VA SWR_ADC2", "ADC3_OUTPUT",
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"VA SWR_ADC3", "ADC4_OUTPUT",
|
|
"VA SWR_MIC0", "DMIC1_OUTPUT",
|
|
"VA SWR_MIC1", "DMIC2_OUTPUT",
|
|
"VA SWR_MIC2", "DMIC3_OUTPUT",
|
|
"VA SWR_MIC3", "DMIC4_OUTPUT",
|
|
"VA SWR_MIC4", "DMIC5_OUTPUT",
|
|
"VA SWR_MIC5", "DMIC6_OUTPUT",
|
|
"VA SWR_MIC6", "DMIC7_OUTPUT",
|
|
"VA SWR_MIC7", "DMIC8_OUTPUT";
|
|
qcom,msm-mbhc-hphl-swh = <1>;
|
|
qcom,msm-mbhc-gnd-swh = <1>;
|
|
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
|
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
|
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
|
|
asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
|
|
asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
|
|
"msm-ext-disp-audio-codec-rx";
|
|
qcom,wsa-max-devs = <2>;
|
|
qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
|
|
qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
|
|
qcom,codec-max-aux-devs = <1>;
|
|
qcom,codec-aux-devs = <&wcd938x_codec>;
|
|
qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
|
|
qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>;
|
|
qcom,cps_threshold_levels = <148 168>;
|
|
qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
|
|
qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
|
|
qcom,cps_lower2_values = <0x0F 0x0F 0x18>;
|
|
qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
|
|
<&lpi_tlmm>, <&bolero>;
|
|
};
|
|
|
|
&q6core {
|
|
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
|
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <133 134>;
|
|
};
|
|
|
|
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
|
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <136>;
|
|
};
|
|
|
|
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
|
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <139 140>;
|
|
};
|
|
|
|
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
|
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
|
&rx_swr_data1_active>;
|
|
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
|
&rx_swr_data1_sleep>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
tx_swr_gpios: tx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
|
|
&tx_swr_data2_active &tx_swr_data3_active>;
|
|
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
|
|
&tx_swr_data2_sleep &tx_swr_data3_sleep>;
|
|
qcom,lpi-gpios;
|
|
qcom,tlmm-gpio = <128 129>;
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
wsa_spkr_en1: wsa_spkr_en1_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&spkr_1_sd_n_active>;
|
|
pinctrl-1 = <&spkr_1_sd_n_sleep>;
|
|
};
|
|
|
|
wsa_spkr_en2: wsa_spkr_en2_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&spkr_2_sd_n_active>;
|
|
pinctrl-1 = <&spkr_2_sd_n_sleep>;
|
|
};
|
|
|
|
wcd938x_rst_gpio: msm_cdc_pinctrl@83 {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wcd938x_reset_active>;
|
|
pinctrl-1 = <&wcd938x_reset_sleep>;
|
|
};
|
|
|
|
clock_audio_wsa_1: wsa_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x309>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_wsa_2: wsa_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30A>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_1: rx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
|
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
|
qcom,codec-lpass-clk-id = <0x30E>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_2: rx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
|
|
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
|
qcom,codec-lpass-clk-id = <0x30F>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_tx_1: tx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30C>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_tx_2: tx_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30D>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_va_1: va_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30B>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_va_2: va_npl_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x310>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&va_cdc_dma_0_tx {
|
|
qcom,msm-dai-is-island-supported = <1>;
|
|
};
|