For the targets not having slave pll, "slave pll unavailable"
warning gets logged on suspend, resume and idle power collapse.
Change pr_warn to pr_debug to avoid extra logging.
Change-Id: I2f06d88f3ea8ceb03e30095439c24a6729daae97
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
Add support for 7nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.
Change-Id: Iac131b9085d5541434f8480c14e7de4c8d014d2e
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated.
Change-Id: I1e45ff0685797bf4dd2e3a52af4753425f31edfc
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
To improve performance margin for DSI's PLL at cold
temperature case, the value of DSIPHY_PLL_PLL_ICPMSET
should be changed from 0x24 to 0x3f.
Change-Id: I139e37e137355c5e8f0b3bebd28b23a09593dd13
Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Panels supporting Cphy use a specific divider
blocks. Add additional divider blocks for byte
and pixel clock output to support DSI CPHY.
Change-Id: I74b3ee2bdd22ae8fa20567fe837e03915537c4fb
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Update clocks names for lagoon target according to clock
plan.
Change-Id: Ibc798a31d4234e4d6925ba9add2bb0ddb55909bc
Signed-off-by: RAJAT GUPTA <rajatgu@codeaurora.org>
Updates the clk get rate check in dsi pll. This fixes
display clock voting for SVS instead of LSVS issue.
Change-Id: Ibdedd8f476d7a38858d18d233517699b61cf76f1
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Reading register of DSI PLL would fail if PLL is not powered
up, so enable DSI PLL power before reading operation.
Change-Id: Ie9933745035392744bb49241342f05a6be9daedc
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Avoid warning of slave pll unavailable for chipsets
not having slave pll.
Change-Id: Id32af235f2fbefa4869b5c8236436e8e6ed84d60
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
In continuous splash use cases, the display is enabled in
the boot-loader. During display kernel probe, to enable clocks,
the rate is calculated by reading the hardware registers before
the corresponding software rate is set. At times when these rates
are nearly equal, the call for set rate never happens. This can
cause abnormal behavior. In this change during hand-off we don't
recalculate the clock rate to ensure the software programs the clock
registers accordingly.
Change-Id: I1dd448fdddb21a64ba48abe080a99f63976635dc
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Add CLK_SET_RATE_NO_REPARENT flag for the software mux clocks in
DSI 14nm PLL driver which is needed for dynamic refresh feature.
Change-Id: I581e8863abb6c2b46263cac83d115c2a3dd8796c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
PLL supply entry is no longer a mandatory property. Do not
report error if this entry is not present.
CRs-Fixed: 2588602
Change-Id: I1d8ff9e7e56f419c6a8984b69f64d61084e6c0f6
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
1.Typecast to avoid distinct pointer type comparison
2.Keep DMA mask aligned with api definition.
3.Add Suffix for literals
4.Remove multfrac func to avoid uncompatible division.
5.64-bit division( operator "/") on 32-bit platforms is not supported.
Using platform independent API's here
Change-Id: I0e7305418e53876bd1adf00c1963f85cbdf980cc
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
In continuous splash use cases, the display is enabled in
the boot-loader. During display kernel probe, to enable clocks,
the rate is calculated by reading the hardware registers before
the corresponding software rate is set. At times when these rates
are nearly equal, the call for set rate never happens. This can
cause abnormal behavior. In this change during hand-off we don't
recalculate the clock rate to ensure the software programs the clock
registers accordingly.
Change-Id: Ibe512067a134856c4f4364f57a80d50214e88397
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Update dynamic dsi clock sequence for 7nm pll, change the register
which is used to store pre-cal code.
Change-Id: I0cd700f65a1dca965372adbda83416dfbbddd60f
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Limit clock rate of shadow VCO clock as normal VCO clock.
For larger bit clock rate gap between switched ones, the clock switching
would fail due to mismatched VCO clock rate between normal VCO clock and
shadow one.
Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change updates the DSI PHY PLL programming for kona target
as per the hardware recommendation.
Change-Id: I706169fb635e72bd0ccd3057107ea749408733d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Changes to incorporate the different clock names for
lito and kona.
Change-Id: I607366f75426a819226aa252819b507dba07109d
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Remove dividers that are not recommended for DSI DPHY mode
when setting up the clock tree for the DSI pixel clock.
Change-Id: I2563a35ece541c1f5b46c72af7bd2cc79e72a90e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Add support for 7nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.
Change-Id: I870f961c7af4d404e61b45a4ad860ffb0e71ae7c
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add support for 10nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.
Change-Id: Ib61bc5dcb5304bc1e3c7568c1419737580da3c88
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Fix possible out-of-bound access and NULL pointer
dereference in SDE and PLL driver.
Change-Id: Ic5c34b3b4c3e983413a0351c38206cf3f3ab3b1f
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change updates SSC offset value according to recent
hardware recommendation.
Change-Id: Ie822ed6ae8e383f93ca91615617dad4b4324b8a0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The divider clocks in the DSI PLL are 1-based and can accept
a value of 0. Set the flags accordingly in the PLL driver.
CRs-Fixed: 2433864
Change-Id: I82361ae3e2119f9e1922153bd5aba6354e8c5442
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Remove the CLK_GET_RATE_NOCACHE flag from all the DP and DSI
pll clocks. This will eliminate the need to recalculate the
clock rates from HW registers when querying the rates for the
PLL clocks. This will ensure that no unclocked register accesses
are done when these clocks are queried while the display core
is power collapsed.
Change-Id: Ia5e993195cadc2bced32c052bb604e9980ecd4d8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
In continuous splash use cases, the display is enabled in
the boot-loader. During display kernel probe, to enable clocks,
the rate is calculated by reading the hardware registers before
the corresponding software rate is set. At times when these rates
are nearly equal, the call for set rate never happens. This can
cause abnormal behavior. In this change during hand-off we don't
recalculate the clock rate to ensure the software programs the clock
registers accordingly.
Change-Id: I421c523ffd48a0cb73d7721c6d74c8e68aa6d9a5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
When continuous splash is enabled, connector states
are not properly updated with the encoder associated
with it. This is by design, so avoid all making
such request there by avoiding unnecessary errors
during the bootup. Fix a handful of warnings in
the PLL definition files
Change-Id: I7f08c5ff80ea2a2bfb4b19f2ea13c8f9cbb833e8
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Ravikanth Tuniki