Change the earlier and later parameters to calculate the time
differene.
CRs-Fixed: 2675079
Change-Id: I113e084da870470b2186c05f64c414a69e741946
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
in_port information we are getting from the UMD and accessing
it directly without validation which might lead to
corruption and device failure.
CRs-Fixed: 2629969
Change-Id: I0a1c57db9b94f9657427872ae6797635c6aed668
Signed-off-by: Tejas Prajapati <tpraja@codeaurora.org>
Some ISP hardware id instances are disabled on some target skus.
Cpas driver has fuse information based on the dtsi entries.
ISP hw driver queries the cpas driver whether hw instance is
supported or not. If ISP hardware is supported on the target then
continue the isp hardware probe.
CRs-Fixed: 2670876
Change-Id: I6b2316d87aeabccbdf74e151e0e25ff77ed6634f
Signed-off-by: Ravikishore Pampana <rpampana@codeaurora.org>
There is chance that release hw run before process cmd workq
which got scheduled as part of config hw. This causes workq
to continue the context though it got released as part of
release hw.
Added a context state check in process cmd workq handler to
avoid submitting request to cdm hardware.
CRs-Fixed: 2670524
Change-Id: I7009d4b60bd97b9f6d46df51790c127a2cf18205
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
When user space detects an error or does not receive
response for a request, Lets do a reset(LDAR) is triggered.
Before LDAR, user space sends flush command to the
kernel space.
In order to debug the cause for this situation and to dump
the information, user space sends a dump command to the
kernel space before sending flush.
As a part of this command, it passes the culprit request id
and the buffer into which the information can be dumped.
Kernel space traverses across the drivers and find the culprit hw
and log about culprit information for OPE.
CRs-Fixed: 2669222
Change-Id: Ida5cbee7a36917f7276a0f9accf2c35f24bf69c9
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Due to non-availability of all clock levels, while downgrading
or upgrading the clock rate, ope is voting for zero clock rate.
Fix issue by voting for nearest non-zero clockrate while
upgrading or downgrading the clock rate.
CRs-Fixed: 2649906
Change-Id: I2f3488084e0aa32ecfa84bcbebad887a1ef8409d
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
If reset irq is not received within allocated time,
check for irq status to confirm if irq is delayed or
reset failed.
In case of irq delay, clear the irq status and mark it
as success.
CRs-Fixed: 2663505
Change-Id: I1b3658e2ada973f531ddba8bc2378b0440c9088a
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
Turn off the flash while flushing if the flushed request
turns off the flash.
CRs-Fixed: 2576732
Change-Id: I546fc6b6ee79f492af905d163515eb19eed78f41
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
TFE driver submit the config packet to cdm and wait for call back.
If call back has not received with in 60ms, then tfe return failure which
cause tfe stream on failure. Some time cdm call back is not coming
due to cdm worker thread execution delay. So add mechanism to check if
cdm worker thread delay happened then wait for some more time
and check it again.
CRs-Fixed: 2664317
Change-Id: I2eb975a2c70b5889238e9cf706c703022f1bf2f5
Signed-off-by: Ravikishore Pampana <rpampana@codeaurora.org>
Added Pdaf support to tfe driver. TFE camif module register
will configure by user space as per the use case. So removing
the camif module register configuration from tfe driver.
Tfe pdaf port bus shares same write master as rdi2, but pdaf
should be configured as line based and proper packer format.
CRs-Fixed: 2664724
Change-Id: Idcf481eefda24e37ffebb58ed1c8d9e9d3ca6241
Signed-off-by: Ravikishore Pampana <rpampana@codeaurora.org>
There is possibility that ope driver gets invalid
number of stripes. Add a check to validate it and
return failure to user-space.
CRs-Fixed: 2664479
Change-Id: Ic80d3376b853e500b793b0b5d051288f2a2640ba
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Add a check to validate DMI command address before writing
DMI in command buffer. This can avoid cdm doing null pointer
de-reference.
CRs-Fixed: 2664479
Change-Id: If99da6fd23f73c1c666cdcec60b0f68eb300425e
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
There is a possibility that the priority variable would
be accessed even for the HEAD node which would result in
out of bound errors, so access the elements of the
structure only if the handler is found.
CRs-Fixed: 2646173
Change-Id: I0540658b9c9487f6e3a4601a488a1add1e790dda
Signed-off-by: Tejas Prajapati <tpraja@codeaurora.org>
CDM workqueue stores the last fifo bl tag done entry
for which it's got scheduled. There is possibility
that flush can execute before workqueue and remove
all the fifo entries. This can skip the work for new
requests if new bl tag matches with last bl tag done
entry and cdm don't send notification to clients.
Add a check to validate fifo list for empty entry
in cdm workqueue function.
CRs-Fixed: 2653649
Change-Id: I788f6d1e4c1c011a2a9ed690ddeff2b1bde0e569
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
OPE is using memhandle to fill bl information.
So, updating the hang dump logic to use memhandle
instead of iova address to fill bl related information.
IOVA address will be fetched from memhandle inside
dump logic.
CRs-Fixed: 2655671
Change-Id: I536aef71050964c985db359662732f26f026c3d8
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
Secure CP control register always assume that it contains 7 bit
mask for each PHY. But this register format is different based on
target. Update secure CP control bitmask generation logic for each
PHY index based on phy_version.
So we have below 3 combinations to handle at SW.
1.Old Titan Targets : 7 bits for each PHY.
2.PHY 1_2_1 : for 4 pHYS 7 bits and for
remaining 2 PHYs 8 bits are reserved.
3.Mimas (PHY 2_0_1): 8 bits for each PHY.
CRs-Fixed: 2624698
Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d
Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org>
Change the clk variable type from int32_t to int64_t
to avoid integer overflow.
CRs-Fixed: 2609090
Change-Id: I9f785ce2c1e45b1e9a238c42e86da1161bf70f75
Signed-off-by: Ravikishore Pampana <rpampana@codeaurora.org>
Increase maximum count of command buffers in a request to support
more number of init packets.
CRs-Fixed: 2652124
Change-Id: I6c85cf5720076c09350b952bc09ed30fbcf27497
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
It is possible that cdm clients get callback from CDM
in sometime due to delay in scheduling CDM workqueue.
Add a logic to detect this delay so that client don't
detect false hang.
CRs-Fixed: 2640897
Change-Id: I1a9fdc1ac5d6bcc1869802793632bf6bf8b4c2ca
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Dump debug registers and irq status register in case of reset
failure.
CRs-Fixed: 2646377
Change-Id: I1acea4761b884d0ffeba9d44e2f0e70d53f1813b
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
Initialize CDM prior to the OPE. This will help to reset
CDM before OPE.
CRs-Fixed: 2646377
Change-Id: I7136cbb04f687e7d5756431731af618718c5a2a7
Signed-off-by: Rishabh Jain <risjai@codeaurora.org>
