From fe7fec2dd55e5a94d016dd1403f0285c752d4a06 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 17 Aug 2021 15:06:38 +0530 Subject: [PATCH] ARM: dts: msm: Add usb3-u1u2-disable for msm-4.19 targets U1 and U2 are intermediate low power states. To avoid any instability issues during bus reset (initiaited by host), we are disabling U1 and U2 by default. Change-Id: I20757cc1e1bb8fd95befd575fc68012fbc8dcfe9 --- qcom/bengal-usb.dtsi | 1 + qcom/khaje-usb.dtsi | 1 + qcom/scuba-usb.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/bengal-usb.dtsi b/qcom/bengal-usb.dtsi index f079a7764bc6..f3f2d38b2f61 100644 --- a/qcom/bengal-usb.dtsi +++ b/qcom/bengal-usb.dtsi @@ -88,6 +88,7 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi index 152729ec9495..0a14f82784ca 100644 --- a/qcom/khaje-usb.dtsi +++ b/qcom/khaje-usb.dtsi @@ -89,6 +89,7 @@ snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; diff --git a/qcom/scuba-usb.dtsi b/qcom/scuba-usb.dtsi index 819e7442f954..1ac6525df4b0 100644 --- a/qcom/scuba-usb.dtsi +++ b/qcom/scuba-usb.dtsi @@ -88,6 +88,7 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed";