duff/android_kernel_motorola_sm6225
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add some param for bq25980 driver

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1.enable ADC_EN for sc8541
2.add cp_switch for bq25980 driver
3.add STATU5 BIT(6) for cp_switch status

Change-Id: I0d754115b67161327f62b79cf023794c255cd5bb
Reviewed-on: https://gerrit.mot.com/2553725
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Wei Xu <xuwei9@lenovo.com>
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
liuzhen authored and tinno65 committed 2023-03-27 01:05:12 -05:00
1 parent 5bacf09647
commit b115dc9ae5
2 files changed
+16 -5
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drivers/power/bq25980_mmi_iio/bq25980_mmi_iio.c
+14 -5
View File
@@ -88,6 +88,7 @@ struct bq25980_state {
bool ce; bool ce;
bool hiz; bool hiz;
bool bypass; bool bypass;
bool cp_switch;//add cp_switch state
u32 vbat_adc; u32 vbat_adc;
u32 vsys_adc; u32 vsys_adc;
@@ -282,7 +283,7 @@ static struct reg_default sc8541_reg_init_val[] = {
{BQ25980_MASK4, 0x00}, {BQ25980_MASK4, 0x00},
{BQ25980_MASK5, 0x00}, {BQ25980_MASK5, 0x00},
{BQ25980_ADC_CONTROL1, 0x00}, {BQ25980_ADC_CONTROL1, 0x80},//enable ADC_EN
{BQ25980_ADC_CONTROL2, 0x06}, //0x26: enable vac1 vac2 adc and vout adc {BQ25980_ADC_CONTROL2, 0x06}, //0x26: enable vac1 vac2 adc and vout adc
}; };
@@ -906,6 +907,7 @@ static int bq25980_get_state(struct bq25980_device *bq,
unsigned int stat2; unsigned int stat2;
unsigned int stat3; unsigned int stat3;
unsigned int stat4; unsigned int stat4;
unsigned int stat5;
unsigned int ibat_adc_msb; unsigned int ibat_adc_msb;
int ret; int ret;
@@ -925,6 +927,10 @@ static int bq25980_get_state(struct bq25980_device *bq,
if (ret) if (ret)
return ret; return ret;
ret = regmap_read(bq->regmap, BQ25980_STAT5, &stat5);
if (ret)
return ret;
ret = regmap_read(bq->regmap, BQ25980_CHRGR_CTRL_2, &chg_ctrl_2); ret = regmap_read(bq->regmap, BQ25980_CHRGR_CTRL_2, &chg_ctrl_2);
if (ret) if (ret)
return ret; return ret;
@@ -944,6 +950,7 @@ static int bq25980_get_state(struct bq25980_device *bq,
state->ce = chg_ctrl_2 & BQ25980_CHG_EN; state->ce = chg_ctrl_2 & BQ25980_CHG_EN;
state->hiz = chg_ctrl_2 & BQ25980_EN_HIZ; state->hiz = chg_ctrl_2 & BQ25980_EN_HIZ;
state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS; state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS;
state->cp_switch = stat5 & BQ25980_STAT5_CP_SWITCH_MASK;
bq->alarm_status.bits.bat_ovp_alarm = stat1 & BQ25980_STAT1_BAT_OVP_ALM_MASK; bq->alarm_status.bits.bat_ovp_alarm = stat1 & BQ25980_STAT1_BAT_OVP_ALM_MASK;
bq->alarm_status.bits.bat_ocp_alarm = stat1 & BQ25980_STAT1_BAT_OCP_ALM_MASK; bq->alarm_status.bits.bat_ocp_alarm = stat1 & BQ25980_STAT1_BAT_OCP_ALM_MASK;
@@ -1296,7 +1303,8 @@ static bool bq25980_state_changed(struct bq25980_device *bq,
old_state.tflt != new_state->tflt || old_state.tflt != new_state->tflt ||
old_state.ce != new_state->ce || old_state.ce != new_state->ce ||
old_state.hiz != new_state->hiz || old_state.hiz != new_state->hiz ||
old_state.bypass != new_state->bypass); old_state.bypass != new_state->bypass ||
old_state.cp_switch != new_state->cp_switch);
} }
static irqreturn_t bq25980_irq_handler_thread(int irq, void *private) static irqreturn_t bq25980_irq_handler_thread(int irq, void *private)
@@ -2197,11 +2205,12 @@ static int bq25980_iio_read_raw(struct iio_dev *indio_dev,
mutex_unlock(&bq->lock); mutex_unlock(&bq->lock);
power_supply_changed(bq->charger); power_supply_changed(bq->charger);
} }
*val1 = bq->alarm_status.status | (bq->fault_status.status << 8); *val1 = bq->alarm_status.status | (bq->fault_status.status << 8) | (state.cp_switch << 18);
pr_err("[%s] get_state fault:0x%02X , alarm:0x%02X\n", pr_err("[%s] get_state fault:0x%02X , alarm:0x%02X , cp_switch:%d\n",
bq->model_name, bq->model_name,
bq->fault_status.status, bq->fault_status.status,
bq->alarm_status.status); bq->alarm_status.status,
state.cp_switch);
} }
break; break;
case PSY_IIO_CURRENT_NOW: case PSY_IIO_CURRENT_NOW:
drivers/power/bq25980_mmi_iio/bq25980_reg.h
+2
View File
@@ -220,6 +220,8 @@
#define BQ25980_STAT4_TDIE_FLT_MASK BIT(2) #define BQ25980_STAT4_TDIE_FLT_MASK BIT(2)
#define BQ25980_STAT4_TDIE_ALM_MASK BIT(1) #define BQ25980_STAT4_TDIE_ALM_MASK BIT(1)
#define BQ25980_STAT5_CP_SWITCH_MASK BIT(6)
//SC8545 //SC8545
#define SC8541_CTRL6_REG 0x40 #define SC8541_CTRL6_REG 0x40