From 79db63a91f9d877e4435c69a4a8ee22c36379602 Mon Sep 17 00:00:00 2001
From: zhangjun10 <zhangj10@motorola.com>
Date: Mon, 29 Nov 2021 14:21:19 +0800
Subject: [PATCH] : arm/dts: i2c change for samsung RN4V bring up

add I2C input-enable
in I2C sleep for rhode nfc

Change-Id: Id86e0d91673aad3d198c2bf7ad9c8864b809c648
Signed-off-by: zhangjun10 <zhangj10@motorola.com>
Reviewed-on: https://gerrit.mot.com/2129648
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Xiangpo Zhao <zhaoxp3@motorola.com>
Submit-Approved: Jira Key
---
 qcom/khaje-rhode-common-overlay.dtsi | 150 +++++++++++++++++++++------
 1 file changed, 117 insertions(+), 33 deletions(-)

diff --git a/qcom/khaje-rhode-common-overlay.dtsi b/qcom/khaje-rhode-common-overlay.dtsi
index 2a0469767b7f..75763e724a77 100644
--- a/qcom/khaje-rhode-common-overlay.dtsi
+++ b/qcom/khaje-rhode-common-overlay.dtsi
@@ -30,24 +30,82 @@
 	};
 };
 
-&qupv3_se1_i2c {
-  #address-cells = <1>;
-  #size-cells = <0>;
-  status = "okay";
-  sec-nfc@27 {
-    compatible = "sec-nfc";
-    reg = <0x27>;
-    sec-nfc,ven-gpio = <&tlmm 69 0x00>;
-    sec-nfc,firm-gpio = <&tlmm 31 0x00>;
-    sec-nfc,irq-gpio = <&tlmm 70 0x00>;
-    sec-nfc,clk_req-gpio = <&tlmm 112 0x00>;
-    interrupt-parent = <&tlmm>;
-    interrupts = <70 0>;
-    interrupt-names = "nfc_irq";
-    pinctrl-names = "nfc_active", "nfc_suspend";
-    pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
-    pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
-  };
+
+&tlmm{
+	capsense_sar_gpio_pins: capsense_sar_gpio_pins {
+		mux {
+			pins = "gpio106";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio106";
+			drive-strength = <2>;
+			bias-pull-up;
+			input-enable;
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins{
+		qupv3_se1_i2c_act: qupv3_se1_i2c_active {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_i2c_sle: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+				input-enable;
+			};
+		};
+	};
+
+	nfc {
+		nfc_clk_req_active {
+			/* active state */
+			mux {
+				/* GPIO 112: NFC CLOCK REQUEST */
+				pins = "gpio112";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio112";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-up;
+			};
+		};
+
+		nfc_clk_req_suspend {
+			/* sleep state */
+			mux {
+				/* GPIO 112: NFC CLOCK REQUEST */
+				pins = "gpio112";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio112";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	};
 };
 
 &soc {
@@ -64,25 +122,51 @@
 		moto,vib-ldo-gpio = <&tlmm 25 0x0>;
 		status = "ok";
 	};
-};
 
-
-&tlmm{
-	capsense_sar_gpio_pins: capsense_sar_gpio_pins {
-		mux {
-			pins = "gpio106";
-			function = "gpio";
-		};
-
-		config {
-			pins = "gpio106";
-			drive-strength = <2>;
-			bias-pull-up;
-			input-enable;
-		};
+	/* I2C Instance */
+	qupv3_se1_i2c: i2c@4a84000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x4a84000 0x4000>;
+		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		dmas = <&gpi_dma0 0 1 3 64 0>,
+			<&gpi_dma0 1 1 3 64 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_i2c_act>;
+		pinctrl-1 = <&qupv3_se1_i2c_sle>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
 	};
+
 };
 
+&qupv3_se1_i2c {
+  #address-cells = <1>;
+  #size-cells = <0>;
+  status = "okay";
+  sec-nfc@27 {
+    compatible = "sec-nfc";
+    reg = <0x27>;
+    sec-nfc,ven-gpio = <&tlmm 69 0x00>;
+    sec-nfc,firm-gpio = <&tlmm 31 0x00>;
+    sec-nfc,irq-gpio = <&tlmm 70 0x00>;
+    sec-nfc,clk_req-gpio = <&tlmm 112 0x00>;
+    interrupt-parent = <&tlmm>;
+    interrupts = <70 0>;
+    interrupt-names = "nfc_irq";
+    pinctrl-names = "nfc_active", "nfc_suspend";
+    pinctrl-0 = <&nfc_int_active &nfc_enable_active &nfc_clk_req_active>;
+    pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend &nfc_clk_req_suspend>;
+    clock-names = "OSC_NFC";
+
+  };
+};
 
 &sdhc_2 {
 	vdd-supply = <&L22A>;