From 6845d36beaf6cd56d84b2fc8cf5a383560f8be62 Mon Sep 17 00:00:00 2001
From: Raghu Ananya Arabolu <rarabolu@quicinc.com>
Date: Wed, 26 Jun 2019 16:52:18 -0700
Subject: [PATCH] ARM: dts: qcom: Remove GMU power levels from GPU dtsi

The GMU power levels are now hardcoded. Remove the device node
binding that defines the set of GMU power levels.

Change-Id: Ib439f20c8c77af38b579c1222a8915231ab26b84
---
 bindings/gpu/adreno-gmu.txt | 28 ----------------------------
 qcom/kona-gpu.dtsi          | 18 ------------------
 2 files changed, 46 deletions(-)

diff --git a/bindings/gpu/adreno-gmu.txt b/bindings/gpu/adreno-gmu.txt
index 062551e63d81..df028c77773c 100644
--- a/bindings/gpu/adreno-gmu.txt
+++ b/bindings/gpu/adreno-gmu.txt
@@ -41,15 +41,6 @@ GMU GDSC/regulators:
 			"gmu_clk", "ahb_clk", "cxo_clk", "axi_clk", "memnoc_clk",
 			"rbcpr_clk"
 
-- qcom,gmu-pwrlevels: device node defines a set of GMU power levels. It has
-		following required properties:
-
-		- compatible : "qcom,gmu-pwrlevels"
-		- qcom,gmu-pwrlevel: a single power level. Each power level has
-		  below properties:
-			- reg: index of the powerlevel (0 = highest perf)
-			- qcom, gmu-freq: GMU frequency for the power level in Hz.
-
 - List of sub nodes, one for each of the translation context banks needed
 		for GMU to access system memory in different operating mode. Currently
 		supported names are:
@@ -98,25 +89,6 @@ gmu: qcom,gmu@2c6a000 {
 	clock-names = "gmu_clk", "ahb_clk", "cxo_clk",
 				"axi_clk", "memnoc_clk", "rbcpr_clk";
 
-	qcom,gmu-pwrlevels {
-
-	      compatible = "qcom,gmu-pwrlevels";
-	      qcom,gpu-pwrlevel@0 {
-	          reg = <0>;
-	          qcom,gmu-freq = <500000000>;
-	      };
-
-	      qcom,gpu-pwrlevel@1 {
-	          reg = <1>;
-	          qcom,gmu-freq = <200000000>;
-	      };
-
-	      qcom,gpu-pwrlevel@2 {
-	          reg = <2>;
-	          qcom,gmu-freq = <0>;
-	      };
-	};
-
 	gmu_user: gmu_user {
 	      compatible = "qcom,smmu-gmu-user-cb";
 	      iommus = <&kgsl_smmu 4>;
diff --git a/qcom/kona-gpu.dtsi b/qcom/kona-gpu.dtsi
index 8a48fb39f789..e3e35a62b9a3 100644
--- a/qcom/kona-gpu.dtsi
+++ b/qcom/kona-gpu.dtsi
@@ -326,24 +326,6 @@
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";
 
-		qcom,gmu-pwrlevels {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			compatible = "qcom,gmu-pwrlevels";
-
-			/* GMU power levels must go from lowest to highest */
-			qcom,gmu-pwrlevel@0 {
-				reg = <0>;
-				qcom,gmu-freq = <0>;
-			};
-
-			qcom,gmu-pwrlevel@1 {
-				reg = <1>;
-				qcom,gmu-freq = <200000000>;
-			};
-		};
-
 		gmu_user: gmu_user {
 			compatible = "qcom,smmu-gmu-user-cb";
 			iommus = <&kgsl_smmu 0x4 0x400>;