From 1e664b6f58f851ad67e7d6f9d36e8421b7621896 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 14 Dec 2023 11:49:00 +0530 Subject: [PATCH] mmc: sdhci-msm: Reset GCC_SDCC_BCR register for SDHC Reset GCC_SDCC_BCR register before every fresh initilazation. This will reset whole SDHC-msm controller, clears the previous power control states and avoids, software reset timeout issues as below. [ 5.458061][ T262] mmc1: Reset 0x1 never completed. [ 5.462454][ T262] mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== [ 5.469065][ T262] mmc1: sdhci: Sys addr: 0x00000000 | Version:0x00007202 [ 5.475688][ T262] mmc1: sdhci: Blk size: 0x00000000 | Blk cnt:0x00000000 [ 5.482315][ T262] mmc1: sdhci: Argument: 0x00000000 | Trn mode:0x00000000 [ 5.488927][ T262] mmc1: sdhci: Present: 0x01f800f0 | Host ctl:0x00000000 [ 5.495539][ T262] mmc1: sdhci: Power: 0x00000000 | Blk gap: 0x00000000 [ 5.502162][ T262] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x00000003 [ 5.508768][ T262] mmc1: sdhci: Timeout: 0x00000000 | Int stat:0x00000000 [ 5.515381][ T262] mmc1: sdhci: Int enab: 0x00000000 | Sig enab:0x00000000 [ 5.521996][ T262] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int:0x00000000 [ 5.528607][ T262] mmc1: sdhci: Caps: 0x362dc8b2 | Caps_1: 0x0000808f [ 5.535227][ T262] mmc1: sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 [ 5.541841][ T262] mmc1: sdhci: Resp[0]: 0x00000000 | Resp[1]:0x00000000 [ 5.548454][ T262] mmc1: sdhci: Resp[2]: 0x00000000 | Resp[3]:0x00000000 [ 5.555079][ T262] mmc1: sdhci: Host ctl2: 0x00000000 [ 5.559651][ T262] mmc1: sdhci_msm: ----------- VENDOR REGISTER DUMP----------- [ 5.566621][ T262] mmc1: sdhci_msm: DLL sts: 0x00000000 | DLL cfg:0x6000642c | DLL cfg2: 0x0020a000 [ 5.575465][ T262] mmc1: sdhci_msm: DLL cfg3: 0x00000000 | DLL usr ctl:0x00010800 | DDR cfg: 0x80040873 [ 5.584658][ T262] mmc1: sdhci_msm: Vndr func: 0x00018a9c | Vndr func2 :0xf88218a8 Vndr func3: 0x02626040. Change-Id: I2c80dee959b26e4d31dd4268087fc3485ffd9d61 Signed-off-by: Sachin Gupta Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 63 ++++++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 5bd590fcc127..a39ba5706c16 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform * driver source file @@ -5042,6 +5042,44 @@ static int sdhci_msm_notify_load(struct sdhci_host *host, enum mmc_load state) return 0; } +static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host) +{ + + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + struct reset_control *reset = msm_host->core_reset; + int ret = -EOPNOTSUPP; + + if (!reset) { + dev_err(dev, "unable to acquire core_reset\n"); + goto out; + } + + ret = reset_control_assert(reset); + if (ret) { + dev_err(dev, "core_reset assert failed %d\n", ret); + goto out; + } + + /* + * The hardware requirement for delay between assert/deassert + * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to + * ~125us (4/32768). To be on the safe side add 200us delay. + */ + usleep_range(200, 210); + + ret = reset_control_deassert(reset); + if (ret) { + dev_err(dev, "core_reset deassert failed %d\n", ret); + goto out; + } + + usleep_range(200, 210); + +out: + return ret; +} + static void sdhci_msm_hw_reset(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -5063,28 +5101,10 @@ static void sdhci_msm_hw_reset(struct sdhci_host *host) host->mmc->cqe_enabled = false; } - ret = reset_control_assert(msm_host->core_reset); - if (ret) { - dev_err(&pdev->dev, "%s: core_reset assert failed, err = %d\n", - __func__, ret); - goto out; - } - - /* - * The hardware requirement for delay between assert/deassert - * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to - * ~125us (4/32768). To be on the safe side add 200us delay. - */ - usleep_range(200, 210); - - ret = reset_control_deassert(msm_host->core_reset); - if (ret) - dev_err(&pdev->dev, "%s: core_reset deassert failed, err = %d\n", - __func__, ret); - + sdhci_msm_gcc_reset(&pdev->dev, host); sdhci_msm_registers_restore(host); msm_host->reg_store = false; -out: + return; } @@ -5411,6 +5431,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) goto pltfm_free; } + sdhci_msm_gcc_reset(&pdev->dev, host); /* Setup Clocks */ /* Setup SDCC bus voter clock. */