From 1bae99c319db1ec16987293519ab3232eba7bddd Mon Sep 17 00:00:00 2001 From: wunan3 Date: Fri, 20 May 2022 16:39:13 +0800 Subject: [PATCH] Devon4G:seperated DVT2/DVT1 sar firmware WHY:need seperated sar firmware HOW:seperated by device tree Change-Id: Iee58c4432362869b0fc6db2d3b31df6ad8c01e34 Signed-off-by: wunan3 Reviewed-on: https://gerrit.mot.com/2274971 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Jianguo Liu Reviewed-by: Wang Wang Submit-Approved: Jira Key --- qcom/khaje-devon-common-overlay.dtsi | 28 ---------------------------- qcom/khaje-devon-dvt2-overlay.dts | 2 +- qcom/khaje-devon-evt-overlay.dts | 27 +++++++++++++++++++++++++++ 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/qcom/khaje-devon-common-overlay.dtsi b/qcom/khaje-devon-common-overlay.dtsi index 070102ea87c1..44b745b7685e 100644 --- a/qcom/khaje-devon-common-overlay.dtsi +++ b/qcom/khaje-devon-common-overlay.dtsi @@ -87,34 +87,6 @@ status = "ok"; }; -&qupv3_se2_i2c { - status = "ok"; - aw9610x_sar@12 { - compatible = "awinic,aw9610x_sar_0"; - reg = <0x12>; - sar-gpio-vcc-enable; - sar-gpio_3v0_en = <&tlmm 67 0x00>; - pinctrl-names = "default"; - pinctrl-0 = <&capsense_sar_gpio_pins>; - interrupt-parent = <&tlmm>; - interrupts = <106 0x02>; - irq-gpio = <&tlmm 106 0x02>; - chip_name = "AW96105"; - sar-num = <0>; - cap_vcc-supply = <&pm6125_l21>; - aw9610x,channel_number = <0x5>; - ch0_name = "Ch0capsense_reference"; - ch1_name = "Ch1capsense_top_left"; - ch2_name = "Ch2capsense_top_right"; - ch3_name = "Ch3capsense_reference"; - ch4_name = "Ch4capsense_bottom"; - ref_channel = <0x9>; - hardware_version = <0>; - aw9610x,using-firmware; - aw9610x,firmware_name = "aw9610x_0"; - }; -}; - &usb0 { dwc3@4e00000 { dr_mode = "otg"; diff --git a/qcom/khaje-devon-dvt2-overlay.dts b/qcom/khaje-devon-dvt2-overlay.dts index de0fade14eab..2f3204b5b0d7 100644 --- a/qcom/khaje-devon-dvt2-overlay.dts +++ b/qcom/khaje-devon-dvt2-overlay.dts @@ -19,7 +19,7 @@ model = "devon"; compatible = "qcom,khaje-devon", "qcom,khaje-moto", "qcom,khaje"; qcom,msm-id = <518 0x10000>; - qcom,board-id = <0 0xA000>; + qcom,board-id = <0 0xB200>; }; &qupv3_se2_i2c { diff --git a/qcom/khaje-devon-evt-overlay.dts b/qcom/khaje-devon-evt-overlay.dts index af5dbd6b9326..942c3debe016 100644 --- a/qcom/khaje-devon-evt-overlay.dts +++ b/qcom/khaje-devon-evt-overlay.dts @@ -22,3 +22,30 @@ qcom,board-id = <0 0xA000>; }; +&qupv3_se2_i2c { + status = "ok"; + aw9610x_sar@12 { + compatible = "awinic,aw9610x_sar_0"; + reg = <0x12>; + sar-gpio-vcc-enable; + sar-gpio_3v0_en = <&tlmm 67 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <&capsense_sar_gpio_pins>; + interrupt-parent = <&tlmm>; + interrupts = <106 0x02>; + irq-gpio = <&tlmm 106 0x02>; + chip_name = "AW96105"; + sar-num = <0>; + cap_vcc-supply = <&pm6125_l21>; + aw9610x,channel_number = <0x5>; + ch0_name = "Ch0capsense_reference"; + ch1_name = "Ch1capsense_top_left"; + ch2_name = "Ch2capsense_top_right"; + ch3_name = "Ch3capsense_reference"; + ch4_name = "Ch4capsense_bottom"; + ref_channel = <0x9>; + hardware_version = <0>; + aw9610x,using-firmware; + aw9610x,firmware_name = "aw9610x_0"; + }; +};